transistor c331
Abstract: c331 transistor C3318 C3317 C331 C3311 C331 datasheet CY7C331 20HC c331 equivalent
Text: CY7C331 Asynchronous Registered EPLD Features • Low power — 90 mA typical ICC quiescent • Twelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — 180 mA ICC maximum — UV-erasable and reprogrammable — One feedback flip-flop with input coming from the
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CY7C331
CY7C331
transistor c331
c331 transistor
C3318
C3317
C331
C3311
C331 datasheet
20HC
c331 equivalent
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transistor c331
Abstract: c331 transistor c331 c331 equivalent C3318 C3319 C3314 c3317 C3311 transistor c331 datasheet
Text: fax id: 6016 1CY7C331 CY7C331 Asynchronous Registered EPLD Features • Low power — 90 mA typical ICC quiescent • Twelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — 180 mA ICC maximum — UV-erasable and reprogrammable
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1CY7C331
CY7C331
transistor c331
c331 transistor
c331
c331 equivalent
C3318
C3319
C3314
c3317
C3311
transistor c331 datasheet
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c331 equivalent
Abstract: C3317 c331-12 c3311 192x pin diagram c331
Text: CY7C331 Asynchronous Registered EPLD • Low power — 90 mA typical ICC quiescent Features • Twelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — 180 mA ICC maximum — UV-erasable and reprogrammable — One feedback flip-flop with input coming from the I/O
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CY7C331
28-pin
c331 equivalent
C3317
c331-12
c3311
192x
pin diagram c331
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L496D
Abstract: 9l reset CY7C331 ST L11922 0423-J
Text: CY7C331 -W C Y P R E S S Asynchronous Registered EPLD Features • TWelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coining from the I/O pin — Independent product term set,
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CY7C331
28-pin
CY7C331
-40TMB
28-Lead
CY7C331â
40WMB
28-Lead
300-Mil)
L496D
9l reset
ST L11922
0423-J
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Untitled
Abstract: No abstract text available
Text: CY7C330 C Y P R E S S •0 Features • Twelve I/O macrocells each having: — registered, three-state I/O pins — input register clock select multi plexer — feed back multiplexer — output enable OE multiplexer • All twelve macrocell state registers
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CY7C330
28-pin,
300-mil
CY7C330â
28QMB
28-Pin
28TMB
28-Lead
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Untitled
Abstract: No abstract text available
Text: Asynchronous Registered EPLD 13 inputs, 12 feedback VO pins, plus 6 shared I/O macrocell feedbacks for a total of 31 true and complementary inpnts High speed: 20 ns maximum tpo Security bit Space-saving 28-pin slim-line DIP package; also available in 28-pin
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28-pin
28-pin
termW22
28-Lead
300-Mil)
CY7C331
001305b
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TCO - 909 F 10 MHz
Abstract: TCO - 909 C335 CY7C335 TCO - 909 F C335A
Text: CY7C335 CYPRESS Features • 100-MHz output registered operation • Twelve I/O macrocells, each having: — Registered, three-state I/O pins — Input and output register clock se lect multiplexer — Feed back multiplexer — Output enable OE multiplexer
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CY7C335
100-MHz
CY7C335â
28-Lead
300-Mil)
40DMB
TCO - 909 F 10 MHz
TCO - 909
C335
TCO - 909 F
C335A
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TCO - 909 F 10 MHz
Abstract: TCO - 909 F CERAMIC LEADLESS CHIP CARRIER C335 CY7C335
Text: CY7C335 CYPRESS Features • 100-MHz output registered operation • Twelve I/O macrocells, each having: — Registered, three-state I/O pins — Input and output register clock se lect multiplexer — Feed back multiplexer — Output enable OE multiplexer
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CY7C335
100-MHz
300-Mil)
CY7C335â
40DMB
28-Lead
40HMB
28-Pin
TCO - 909 F 10 MHz
TCO - 909 F
CERAMIC LEADLESS CHIP CARRIER
C335
CY7C335
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C3317
Abstract: L1190 CY7331
Text: Asynchronous Registered EPLD Features • TWelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coming from the I/O pin — Independent product term set, reset, and clock inputs on all
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28-pin
28-Lead
28-Lead
300-Mil)
CY7C331
0Dlb56b
C3317
L1190
CY7331
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CY7C342
Abstract: No abstract text available
Text: CY7C342 CYPRESS SEMICONDUCTOR 128-Macrocell MAX EPLDs The speed and density of the CY7C342 allows it to be used in a wide range of applications, from replacement of large amounts of 7400-series TTL logic, to complex controllers and multifunction chips. With greater than 25 times the
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CY7C342
128-Macrocell
7400-series
20-pin
CY7C342
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Untitled
Abstract: No abstract text available
Text: K? PRELIMINARY ? Js CYPRESS SEMICONDUCTOR = 192-Macrocell MAX EPLD software or by the model shown in Features Logic Array Blocks • 192 macrocells in 12 LABs • 8 dedicated inputs, 64 bidirectional I/O pins • Programmable interconnect array • 384 expander product terms
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192-Macrocell
84-pin
CY7C341.
CY7C341-30RC
tAC02
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61S11
Abstract: No abstract text available
Text: fax id: 6016 CY7C331 CYPRESS Asynchronous Registered EPLD Features • Twelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coming from the I/O pin — Independent product term set, reset, and clock in
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28-pin
CY7C331-30DMB
CY7C331-30HMB
CY7C331-30LMB
CY7C331-30QMB
CY7C331--
30TMB
CY7C331-30WMB
CY7C331-40DMB
CY7C331
61S11
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tsl-3
Abstract: gear 49t 7C341-40 CY7C341 CY7C341B 38-00137-F 7C341 dd1307h
Text: CY7C341 CY7C341B if CYPRESS Features • 192 macrocells in 12 LABs • 8 dedicated inputs, 64 bidirectional I/O pins • 0.8-micron double-metal CMOS EPROM technology CY7C341 • Advanced 0.65-micron CMOS technology to increase performance (CY7C341B) • Programmable interconnect array
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CY7C341
CY7C341B
192-Macrocell
CY7C341)
65-micron
CY7C341B)
84-pin
TheCY7C341
andCY7C341Bare
CY7C341/
tsl-3
gear 49t
7C341-40
CY7C341B
38-00137-F
7C341
dd1307h
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2SUR
Abstract: CY7C331 L1190 C3317
Text: CY7C331 ¿F C Y P R E S S Features • TWelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coining from the I/O pin — Independent product term set, reset, and clock inpnts on all
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CY7C331
28-pin
40HMB
CY7C331â
40LMB
28-Square
40QMB
2SUR
L1190
C3317
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7c331
Abstract: c33115
Text: 7C331:1/92 Revision: December 1992 fax id: 6016 CY7C331 V CYPRESS Asynchronous Registered EPLD • Low power Features — 90 mA typical lcc quiescent • Twelve I/O macro cel Is each having: — One state flip-flop with an XOR sum-of-products input — 180 mA lcc maximum
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7C331
28-pights.
CY7C331
28-Lead
300-Mil)
MIL-STD-1835
15Config
c33115
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CY7C335-50WMB
Abstract: C3359
Text: = # CY7C335 C YPRESS Universal Synchronous EPLD Features • 100-MHz output registered operation • Twelve I/O macrocells, each having: — Registered, three-state I/O pins — Input and output register clock se lect multiplexer — Feed back multiplexer
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14-controlled)
terms--32
10-ns
28-pin,
300-mil
CY7C335
100-MHz
28-Lead
300-Mil)
28-Pin
CY7C335-50WMB
C3359
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Untitled
Abstract: No abstract text available
Text: CY7C341 CY7C341B ^CYPRESS Features • 192 macrocells in 12 LABs • 8 dedicated inputs, 64 bidirectional I/O pins • 0.8-micron double-metal CMOS EPROM technology CY7C341 • Advanced 0.65-micron CMOS technology to increase performance (CY7C341B) • Programmable interconnect array
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CY7C341
CY7C341B
CY7C341)
65-micron
CY7C341B)
84-pin
TheCY7C341
CY7C341Bare
CY7C341/
CY7C341Bowed
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