143MHZ Search Results

CA10

Abstract: V54C3256804VA
Contextual Info: MOSEL VITELIC V54C3256804VA HIGH PERFORMANCE 3.3 VOLT 32M X 8 SYNCHRONOUS DRAM 4 BANKS X 8Mbit X 8 PRELIMINARY -7PC -7 -8PC -8 System Frequency fCK 143MHz 143MHz 125MHz 125MHz Clock Cycle Time (tCK3) 7 ns 7 ns 8 ns 8 ns Clock Access Time (tAC3) CAS Latency = 3

V54C365804VC

Contextual Info: MOSEL VITELIC V54C365804VC HIGH PERFORMANCE 143/133/125 MHz 3.3 VOLT 8M X 8 SYNCHRONOUS DRAM 4 BANKS X 2Mbit X 8 PRELIMINARY 7 75 8PC 8 System Frequency fCK 143MHz 133MHz 125 MHz 125 MHz Clock Cycle Time (tCK3) 7 ns 7.5 ns 8 ns 8 ns Clock Access Time (tAC3) CAS Latency = 3

Contextual Info: W971632AF 256K x 32 bit x 2 Banks SGRAM Features • • • • • • • • • • • • • • JEDEC standard 3.3V power supply Up to 143MHz clock frequency 262,144 words x 2 banks x 32 bits 1 Bank Select, Row Address A0~A9, Column Address A0~A7

Contextual Info: NSTS1428-E Apr. 2013 NewJRC SAW FILTER NSTS1428 Application 143MHz STD-T99 Electrical Specification: Table 1 The device characteristics are measured in the circuit shown in Fig.1. Table 1. Electrical Specifications Item JRC Simulation Spec. Typ. Input and Output Impedance

A43L2616

Abstract: A43L2616V
Contextual Info: A43L2616 1M X 16 Bit X 4 Banks Synchronous DRAM Features n n n n n Clock Frequency: 166MHz @ CL=3 143MHz @ CL=3 n Burst Read Single-bit Write operation n DQM for masking n Auto & self refresh n 64ms refresh period 4K cycle n 54 Pin TSOP (II) JEDEC standard 3.3V power supply

KM4132G271B

Contextual Info: KM4132G271B CMOS SGRAM Revision History Revision 2.4 May 1998 • Added KM4132G271B-7 product(143MHz @ CL =3). Revision 2.3 (March 1998) • Added Reverse Type Package in ODERING INFORMATION and PIN CONFIGURATION. • Removed KM4132G271B-H/12 product(-H : 100MHz @ CL =2, -12 : 83MHz @ CL=3).

ba 5888

Abstract: V54C3256164VA
Contextual Info: MOSEL VITELIC V54C3256164VA HIGH PERFORMANCE 3.3 VOLT 16M X 16 SYNCHRONOUS DRAM 4 BANKS X 4Mbit X 16 PRELIMINARY -7 -8PC -8 System Frequency fCK 143MHz 125 MHz 125 MHz Clock Cycle Time (tCK3) 7 ns 8 ns 8 ns Clock Access Time (tAC3) CAS Latency = 3 5.4 ns

Contextual Info: A43L3616A Preliminary 2M X 16 Bit X 4 Banks Synchronous DRAM Document Title 2M X 16 Bit X 4 Banks Synchronous DRAM Revision History History Issue Date Remark 0.0 Initial issue August 7, 2007 Preliminary 0.1 Change clock frequency from 133MHz to 143MHz at 7ns cycle

CA10

Abstract: V54C365804VB
Contextual Info: MOSEL VITELIC V54C365804VB HIGH PERFORMANCE 143/133/125 MHz 3.3 VOLT 8M X 8 SYNCHRONOUS DRAM 4 BANKS X 2Mbit X 8 PRELIMINARY 7 75 8PC 8 System Frequency fCK 143MHz 133MHz 125 MHz 125 MHz Clock Cycle Time (tCK3) 7 ns 7.5 ns 8 ns 8 ns Clock Access Time (tAC3) CAS Latency = 3

Contextual Info: I =¥= = = = ’= Advance IBM0664404ET3A IBM0664804ET3A 64Mb Double Data Rate Synchronous DRAM Special Features • 125MHz max clock freq @ CAS Latency=2 • 133MHz max clock freq @ CAS Latency=2.5 • 143MHz max clock freq @ CAS Latency=3 • On-chip DLL to align output data with input clock

CA10

Abstract: V54C365804VC
Contextual Info: V54C365804VC HIGH PERFORMANCE 143/133/125 MHz 3.3 VOLT 8M X 8 SYNCHRONOUS DRAM 4 BANKS X 2Mbit X 8 MOSEL VITELIC PRELIMINARY 7 75 8PC 8 System Frequency fCK 143MHz 133MHz 125 MHz 125 MHz Clock Cycle Time (tCK3) 7 ns 7.5 ns 8 ns 8 ns Clock Access Time (tAC3) CAS Latency = 3

ir tk 2238

Abstract: IT191 CA10 V54C365804VC tk 2238 7777777Z
Contextual Info: M O S E L V IT E L IC V54C365804VC HIGH PERFORMANCE 143/133/125 MHz 3.3 VOLT8MX8SYNCHRONOUS DRAM 4 BANKS X 2Mbit X 8 PRELIMINARY 7 75 8PC 8 System Frequency fCK 143MHz 133MHz 125 MHz 125 MHz Clock Cycle Tim e (tcK 3 ) 7 ns 7.5 ns 8 ns 8 ns Clock Access Tim e (tAC3) CAS Latency = 3

AS4C8M32S-7BCN

Abstract: AS4C8M32S
Contextual Info: AS4C8M32S Revision History AS4C8M32S- 90 Ball TFBGA PACKAGE Revision Rev 1.0 Rev 1.1 Rev 2.0 Details Preliminary datasheet Added 166MHz option -6 clock cycle time Typing error page 1 – fast clock rate error 133MHz should be 143MHz Typing error - Frequency in Table 2. Ordering information

A43L3616A

Contextual Info: A43L3616A/A43L4608A 2M x 16 Bit x 4 Banks, 4M X 8 Bit X 4 Banks Synchronous DRAM Preliminary Document Title 2M X 16 Bit X 4 Banks Synchronous DRAM Revision History History Issue Date Remark 0.0 Initial issue August 7, 2007 Preliminary 0.1 Change clock frequency from 133MHz to 143MHz at 7ns cycle

CA10

Abstract: V54C365804VD
Contextual Info: MOSEL VITELIC V54C365804VD L HIGH PERFORMANCE 143/133/125 MHz 3.3 VOLT 8M X 8 SYNCHRONOUS DRAM 4 BANKS X 2Mbit X 8 PRELIMINARY 7 75 8PC 8 System Frequency (fCK) 143MHz 133MHz 125 MHz 125 MHz Clock Cycle Time (tCK3) 7 ns 7.5 ns 8 ns 8 ns Clock Access Time (tAC3) CAS Latency = 3

CA10

Abstract: V54C3256804VA
Contextual Info: V54C3256804VA HIGH PERFORMANCE 3.3 VOLT 32M X 8 SYNCHRONOUS DRAM 4 BANKS X 8Mbit X 8 MOSEL VITELIC PRELIMINARY -7 -8PC -8 System Frequency fCK 143MHz 125MHz 125MHz Clock Cycle Time (tCK3) 7 ns 8 ns 8 ns Clock Access Time (tAC3) CAS Latency = 3 5.4 ns 6 ns

Contextual Info: A43L3616A Series 2M x 16 Bit x 4 Banks Synchronous DRAM Preliminary Document Title 2M x 16 Bit x 4 Banks Synchronous DRAM Revision History History Issue Date Remark 0.0 Initial issue August 7, 2007 Preliminary 0.1 Change clock frequency from 133MHz to 143MHz at 7ns cycle

CA10

Abstract: V54C3256404VA t-16
Contextual Info: MOSEL VITELIC V54C3256404VA HIGH PERFORMANCE 3.3 VOLT 64M X 4 SYNCHRONOUS DRAM 4 BANKS X 16Mbit X 4 PRELIMINARY -7 -8PC -8 System Frequency fCK 143MHz 125 MHz 125 MHz Clock Cycle Time (tCK3) 7 ns 8 ns 8 ns Clock Access Time (tAC3) CAS Latency = 3 5.4 ns

Contextual Info: M EM O RY SCs FUNCTION GUIDE 1. GRAPHIC BUFFER MEMORY PRODUCT TREE - KM4132QS71A : Up to 143MHz, 2nd Generation * SYNCHRONOUS DRAM PRODUCT TREE 64M bit , IBM * 4 :U p to 1 5 0 M H z SM X B : Up to 150MHz 4 M X 16 : Up to 150MHz Under D evelopm ent 152 ELECTRONICS

Contextual Info: A43L2616-PH Series 1M X 16 Bit X 4 Banks Synchronous DRAM Features n n n n n Clock Frequency: 166MHz @ CL=3 143MHz @ CL=3 n Burst Read Single-bit Write operation n DQM for masking n Auto & self refresh n 64ms refresh period 4K cycle n 54 Pin TSOP (II) JEDEC standard 3.3V power supply

KMM966G512BQ

Abstract: km4132g
Contextual Info: SGRAM MODULE KMM965G512BQ P N / KMM966G512BQ(P)N Revision History Revision 2.5 (July 1998) • Added -7(143MHz) speed product. • Changed SPD data, Byte #62 from 02h to 00h. • Changed Pin #43 from DQ34 to DQ35 in PIN CONFIGURATIONS. Revision 2.4 (June 1998)

V54C3256404VA

Abstract: CA10
Contextual Info: MOSEL VITELIC V54C3256404VA HIGH PERFORMANCE 3.3 VOLT 64M X 4 SYNCHRONOUS DRAM 4 BANKS X 16Mbit X 4 PRELIMINARY -7 -8PC -8 System Frequency fCK 143MHz 125 MHz 125 MHz Clock Cycle Time (tCK3) 7 ns 8 ns 8 ns Clock Access Time (tAC3) CAS Latency = 3 5.4 ns

1013060/1

Abstract: 2mbit HY57V281620HCT-H HY57V281620HCT-6 HY57V281620HCT-7 HY57V281620HCT-8 HY57V281620HCT-K HY57V281620HCT-P HY57V281620HCT-S
Contextual Info: 0.1 : Hynix Change 0.2 : 143Mhz Add, Burst read single write mode correction HY57V281620HC L/S T 4 Banks x 2M x 16bits Synchronous DRAM DESCRIPTION The Hynix HY57V281620HC(L/S)T is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory applications

Contextual Info: M OSEL VITELIC V54C365804VB HIGH PERFORMANCE 143/133/125 MHz 3.3 V O LT 8M X 8S Y N C H R O N O U S DRAM 4 BANKS X 2M bit X 8 PRELIMINARY 7 75 8PC 8 System Frequency fCK 143MHz 133MHz 125 MHz 125 MHz Clock Cycle Tim e (tcK 3 ) 7 ns 7.5 ns 8 ns 8 ns Clock Access Tim e (tAC3) CAS Latency = 3