111MHZ Search Results

Contextual Info: ADVANCED INFORMATION P L D 2 2 V 1 0 -7 High Performance 10-Macrocell CMOS PLD • High Speed Upgrade to BiCMOS/Bipolar 22V 10 and CMOS Equivalents ■ Global Asynchronous Clear and Synchronous Preset P-terms. ■ tpp 7.5ns, 111MHz with Feedback ■ 1-Micron CHMOS EPROM Technology

Contextual Info: DATA SHEET 256M bits SDRAM Bare Chip ECS2532EECN-A 8M words x 32 bits Features • Density: 256M bits • Organization  2M words × 32 bits × 4 banks • Package: Bare chip • Power supply: VDD, VDDQ = 1.8V ± 0.1V • Clock frequency: 111MHz (max.)

LBS11101

Contextual Info: 111MHz SAW Filter 3MHz Bandwidth China Electronics Technology Group Corporation No.26 Research Institute SIPAT Co., Ltd. Part Number:LBS11101 www.sipatsaw.com Specifications Parameter Unit Minimum Typical Maximum Center Frequency MHz 111.2 111.3 111.4 Insertion Loss

Contextual Info: PRELIMINARY DATA SHEET 128M bits SDRAM Bare Chip ECS1232ECCN-A 4M words x 32 bits Features • Density: 128M bits • Organization  1M words × 32 bits × 4 banks • Package: Bare chip • Power supply: VDD, VDDQ = 1.8V ± 0.1V • Clock frequency: 111MHz (max.)

Contextual Info: K4M28163PF - R B G/F Mobile-SDRAM 2M x 16Bit x 4 Banks Mobile SDRAM in 54CSP FEATURES GENERAL DESCRIPTION • 1.8V power supply. The K4M28163PF is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNG’s high performance CMOS technology. Synchronous design allows precise cycle control with the

Contextual Info: K4M64163PH - R B G/F Mobile-SDRAM 1M x 16Bit x 4 Banks Mobile SDRAM in 54CSP FEATURES GENERAL DESCRIPTION • 1.8V power supply. The K4M64163PH is 67,108,864 bits synchronous high data • LVCMOS compatible with multiplexed address. rate Dynamic RAM organized as 4 x 1,048,576 words by 16 bits,

K4M56163PG

Abstract: 54-FBGA
Contextual Info: K4M56163PG - R B E/G/C/F Mobile SDRAM 4M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA FEATURES GENERAL DESCRIPTION • 1.8V power supply. The K4M56163PG is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 4,196,304 words by 16 bits, fabricated with SAMSUNG’s high performance CMOS technology. Synchronous design allows precise cycle control with the

K4M283233H

Contextual Info: K4M283233H - F H N/G/L/F Mobile SDRAM 1M x 32Bit x 4 Banks Mobile SDRAM in 90FBGA FEATURES GENERAL DESCRIPTION • 3.0V & 3.3V power supply. The K4M283233H is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 32 bits,

Contextual Info: mult_vgen_v1.0.fm Page 1 Wednesday, October 13, 1999 9:03 AM Variable Parallel Virtex Multiplier V1.0.2 October 15, 1999 Product Specification R Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax: +1 408-559-7114 E-mail: coregen@xilinx.com

LF9502

Abstract: LMU217 ACCM 5 pin digital video mixer - tbc power supply 5 Volt LF3347 9027 scl110 LF3310 LF3311
Contextual Info: Company Profile LOGIC Devices Incorporated develops and markets high-performance integrated circuits that are utilized in a wide range of video and medical imaging processing, telecommunications, computing and military smart weapon applications. LOGIC Devices is commited to providing its customers with the highest performing

PLSI 1016-60LJ

Abstract: PAL 007 pioneer pal16r8 programming algorithm PAL 008 pioneer lattice 1016-60LJ ISP Engineering Kit - Model 100 PLSI-2064-80LJ GAL16v8 programmer schematic GAL programming Guide ispLSI 2064-80LT
Contextual Info: Lattice Semiconductor Data Book 1996 Click on one of the following choices: • Table of Contents • Data Book Updates & New Products • Go to Main Menu 1996 Lattice Semiconductor Corporation. All rights reserved. ispLSI and pLSI Product Index Pins Density

24-Pin Plastic DIP

Abstract: e2cmos technology pioneer corporation
Contextual Info: Introduction to ispGDXV , ispGDX and ispGDS Families TM TM TM Introduction Lattice Semiconductor Corporation, the pioneer of nonvolatile E2CMOS in-system programmable ISP logic, has now expanded the application of ISP PLDs to include programmable switching, interconnect and jumper functions with the ispGDX and the ispGDS devices. In-system

22V10 PAL CMOS device

Abstract: Pal programming 22v10 29MA16 Vantis GAL16V8 16v8d 22v10 pal 20LV8D 16v8 PLD 74xx244 20V8
Contextual Info: Introduction to GAL and PAL Devices ® output drive GAL16VP8 and GAL20VP8 , “zero power” operation (GAL16V8Z/ZD and GAL20V8Z/ZD), and insystem programmability (ispGAL22V10). Overview Lattice/Vantis, the inventor of the Generic Array Logic (GAL®) and Programmable Array Logic™ (PAL®) families of low density, E2CMOS® PLDs is the leading supplier

M12S16161A

Abstract: M12S16161A-7BG M12S16161A-7TG
Contextual Info: ESMT M12S16161A SDRAM 512K x 16Bit x 2Banks Synchronous DRAM FEATURES z z z z z z z z z GENERAL DESCRIPTION JEDEC standard 2.5V power supply LVTTL compatible with multiplexed address Dual banks operation MRS cycle with address key programs CAS Latency 2 & 3

PPC405EP bsdl

Abstract: PPC405EP transistor w04 ppc405ep-3lb266c L16 eeprom smt w04 w04 75 405EP ns16750 PPC405EP-3GB133CZ
Contextual Info: Part Number PPC405EP Revision 1.07 – September 10, 2007 PPC405EP Data Sheet PowerPC 405EP Embedded Processor Features • • • • • • AMCC PowerPC 405 32-bit RISC processor core operating up to 333MHz with 16KB Dand I-caches PC-133 synchronous DRAM SDRAM interface

EDS2532EEBH-9A

Contextual Info: PRELIMINARY DATA SHEET 256M bits SDRAM EDS2532EEBH-9A 8M words x 32 bits Description Pin Configurations The EDS2532EEBH is a 256M bits SDRAM organized as 2,097,152 words × 32 bits × 4 banks. All inputs and outputs are synchronized with the positive edge of the

k4m641633

Abstract: K4M641633K 54balls
Contextual Info: K4M641633K - R B N/G/L/F Mobile-SDRAM 1M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA FEATURES GENERAL DESCRIPTION • 3.0V & 3.3V power supply. The K4M641633K is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 16 bits,

adv7499

Abstract: adv7402a LT 525I ADV7402 ADV7403 l e d colour tv circuit diagram P2401 av btr hex map 2N101 720P
Contextual Info: a ADV7403 Integrated Multi-Format SDTV/HDTV Video Decoder and RGB Graphics Digitizer DATASHEET MANUAL January 2007 Confidential NDA Required ADV7403 1 INTRODUCTION . 1

Contextual Info: N128R3225GAK2 1M x 32Bit x 4Banks Double Data Rate Synchronous DRAM DISCRIPTION The N128R3225GAK2 is 134,217,728 bits of double data rate synchronous dynamic RAM organized as 4 x 1,048,576 bits by 32 I/Os. Synchronous features with Data Strobe allow extremely high performance up to 400M bps/pin. I/O transactions are possible on both

pioneer corporation

Contextual Info: Introduction to ispGDXV, ispGDX and ispGDS Families ® ® November 2003 Introduction Lattice Semiconductor Corporation, the pioneer of non-volatile E2CMOS® in-system programmable ISP logic, has now expanded the application of ISP PLDs to include programmable switching, interconnect and jumper functions with the ispGDX and the ispGDS devices. In-system programmability allows for real-time programming, less

LF3320

Abstract: LF3321
Contextual Info: LF3321 Horizontal Digital Image Filter DEVICES INCORPORATED Improved Performance FEATURES Selectable 16-bit Data Output with UserDefined Rounding and Limiting Supports Interleaved Data Streams Supports Decimation up to 16:1 for Increasing Number of Filter Taps

LF3311

Abstract: 743H LF3310 LF3320 RV15 VCF5 VCF9
Contextual Info: LF3311 Horizontal / Vertical Digital Image Filter DEVICES INCORPORATED Improved Performance FEATURES 8 Vertical Filter Taps Two Operating Modes: Dimensionally Separate and Orthogonal Supports Interleaved Data Streams Horizontal Filter Supports Decimation up to

oneDRAM

Abstract: 133MHz 640M 111MHz KJXX
Contextual Info: One-DRAMTM Code Information 1/2 Last Updated : August 2009 KJXXXXXXXX - XXXXXXX 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 12. Package (AG01000 PKG SPEC Reference) A : FBGA (Lead-Free, Halogen-Free) S : FBGA (Lead-Free) 1. Memory (K) 2. OneDRAMTM : J 13. Temp, Power

xilinx TURBO decoder

Abstract: DS275 Turbo Code LogiCORE IP License Terms XC2V500 XC2VP20 Turbo decoder Xilinx RSC11
Contextual Info: 3GPP2 Turbo Decoder v1.0 DS275 April 28, 2005 Product Specification Features Applications • Drop-in module for Spartan -3, Spartan-3E, This version of the TCC Turbo Convolution Code decoder is designed to meet the 3GPP2 mobile communication system specification [1].