05T5372 Search Results

ep512 dc

Contextual Info: ALTERA CORP EP512 S4E I> . • QST537S Ü001117 S I ' J. ■.* M 2 MACROCELL EPLD w w m m FEATURES GENERAL DESCRIPTION High Performance logic replacement for TTL and 74HC or 74HCT SSI and MSI logic. High Speed, tpd = 25ns, and 40MHz operating frequency. "Zero Power" 150 //A Standby Current .

ALTERA EP

Abstract: I7232 MIL-STD-883-compliant
Contextual Info: EP1810 EPLD Features • High-performance, 48-macrocell Classic EPLD Combinatorial speeds with tPD as low as 20 ns Counter frequencies of up to 50 MHz Pipelined data rates of up to 62.5 MHz Programmable I/O architecture with up to 64 inputs or 48 outputs The following devices are pin-, function-, and programming filecompatible: EP1810, EP1810T, and EP1810 MIL-STD-883-compliant

altera ep900

Abstract: EP900 74HC EP910 altera EP910 ep900-2 ep9003
Contextual Info: ALTERA 24E D CO R P • 05^5375 GOOllDD r r ^ «nom s 24-M A C R O C E LL EPLO t 7 I -^ -4 7 EP900 FEATURES GENERAL DESCRIPTION • • • • • • • The Altera EP900 is a pin-compatible version of the popular EP910 Erasable Programmable Logic Device EPLD . Available in 40-pin DIP and 44-pln

Contextual Info: M A X 9000 Programmable Logic Device Family Data Sheet March 1995, ver. 2 High-performance EEPROM-based programmable logic devices PLDs built on third-generation Multiple Array MatriX (MAX) architecture Fabricated on 0.65-micron CMOS technology High-density EPLD family ranging from 6,000 usable (12,000

EPM7032

Contextual Info: EPM7032 EPLD M . 32-Macrocell Programmable Logic Device September 1993, ver. 3 Features Data Sheet □ □ □ □ □ □ □ □ High-performance, erasable CMOS EPLD based on second-generation MAX architecture 600 usable gates Combinatorial speeds with t PD = 7.5 ns

EPM5192

Abstract: EPM5192A J-Lead, QFP ceramic 100-Pin Package Pin-Out Diagram A1176 d1072 K66-1 EPM5192-1
Contextual Info: EPM5192 EPLD Features 11 • ■ ■ ■ Figure 20. EPM5192 Package Pin-Out Diagrams Package outlines not drawn to scale. See Tables 8 and 9 in this data sheet fo r pin-out information. Windows in ceramic packages only. 90005005 22 £ So 2 2 cu 5 ooaa o nnnnnnnnnnnnnnn

EP600IPC-45

Abstract: 5962-8686401la ep600i Altera Classic EPLDs altera ep610
Contextual Info: ANbi^n^ EP600I Classic EPLD Data Sheet Supplement March 1995, ver. 2 This data sheet supplement should be used together with the Classic Family Data Sheet and the Altera Device Package Outlines Data Sheet in the current data book. Features ^ □ □ □ □

r12n10

Abstract: EMP7032 max7000
Contextual Info: Includes MAX7000E M A Y IVI M A 7 0 0 0 / UUU Programmable Logic Device Family March 1995, ver. 3 Features. Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance CMOS EEPROM devices based on secondgeneration Multiple Array MatriX MAX architecture

Contextual Info: EP600 EPLD t i d = n & 16-Macrocell Device \ June 1993, ver. 1 Data Sheet Supplement 16-macrocell Classic EPLD - Combinatorial speeds with tPD = 45 ns Counter frequencies up to 222 MHz Pipelined data rates up to 263 MHz □ Programmable I/O architecture with up to 20 inputs or 16 outputs

EPM5130

Contextual Info: A L TE RA CORP □5*15372 0 0 D 2 1 4 2 4bT « A L T 47E D 'P f D - 0 l EPM5016 to EPM5192 EPLDs High-Speed, High-Density MAX 5000 Devices Data Sheet September 1991, ver. 2 Features □ □ □ □ □ □ Complete family of CMOS EPLDs solves design tasks ranging from

EPX880-10

Abstract: altera epx740
Contextual Info: FLASHIogic Programmable Logic Device Family Features. • ■ Prelim inary Information ■ ■ ■ Formerly Intel's FLEXlogic iFX family High-performance programmable logic device (PLD) family SRAM-based logic w ith shadow EPROM or FLASH memory elements fabricated on 0.6- and 0.8-micron CMOS technology

altera EP600

Abstract: ep800 EP600 EP600 programming EP610 "pin compatible" EP610 74HC GOG111S 16 macrocells 05T5372
Contextual Info: ALTERA CORP 24E D 05^5372 0001113 5 rr-tUrG-iFi iu I m m m :.SSI6-M ACROCELL EPLD FEATURES GENERAL DESCRIPTION • High density logic replacement for TTL and 74HC. • Functional and pin compatible with the Altera EP600. • High speed, tpd = 45 ns. • Asynchronous clocking of ail registers or banked

half adder ic

Abstract: ic number of half adder half adder ic number EP3123 D5AC32430 D5AC324 D5AC312-25
Contextual Info: EP312 & EP324 Classic EPLDs A p ril 19 95, ver. 1 Features D ata S h e e t • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ General Description High-performance EPLDs with 12 macrocells EP312 or 24 macrocells (EP324) Combinatorial speeds as fast as 25 ns

EPM7128

Abstract: EPM7128 EPLD EPM7128-15 altera max epm7128 EPM7128-10 EPM7128 PLCC epm71284 D4038 EPM7128-12
Contextual Info: A L TE RA CORP bôE D • OSASTE 0003244 GÜD « A L T EPM7128 E P LD Features ^ □ □ □ □ □ H igh -d en sity CM O S EP LD b a se d on secon d -gen eration M AX architecture 2,500 usable gates Com binatorial speeds with tPD = 10 ns Counter frequencies up to 100 MHz