39S256160DT-7
Abstract: HYB39S256400D PC133-222-520 PC166
Text: Data Sheet, Rev. 1.02, Feb. 2004 HYB39S256400D[C/T] L HYB39S256800D[C/T](L) HYB39S256160D[C/T](L) 256-MBit Synchronous DRAM SDRAM Memory Products N e v e r s t o p t h i n k i n g . Edition 2004-02 Published by Infineon Technologies AG, St.-Martin-Strasse 53,
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HYB39S256400D
HYB39S256800D
HYB39S256160D
256-MBit
P-TSOPII-54
GPX09039
10072003-13LE-FGQQ
HYB39S256
TFBGA-54
39S256160DT-7
PC133-222-520
PC166
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Untitled
Abstract: No abstract text available
Text: GM72V66441ET/ELT 4,194,304 WORD x 4 BIT x 4 BANK SYNCHRONOUS DYNAMIC RAM Description The GM72V66441ET/ELT is a synchronous dynamic random access memory comprised of 67,108,864 memory cells and logic including input and output circuits operating synchronously
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GM72V66441ET/ELT
GM72V66441ET/ELT
BA0/A13
BA1/A12
TTP-54D)
TTP-54D
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GM72V66841ET
Abstract: No abstract text available
Text: GM72V66841ET/ELT 2,097,152 WORD x 8 BIT x 4 BANK SYNCHRONOUS DYNAMIC RAM Description The GM72V66841ET/ELT is a synchronous dynamic random access memory comprised of 67,108,864 memory cells and logic including input and output circuits operating synchronously
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GM72V66841ET/ELT
GM72V66841ET/ELT
BA0/A13
BA1/A12
TTP-54D)
TTP-54D
GM72V66841ET
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w986432dh
Abstract: 2262 decoder
Text: PRELIMINARY W986432DH 512K x 4 BANKS × 32 BITS SDRAM GENERAL DESCRIPTION W986432DH is a high-speed synchronous dynamic random access memory SDRAM , organized as 512K words × 4 banks × 32 bits. Using pipelined architecture and 0.175 µm process technology,
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W986432DH
W986432DH
2262 decoder
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GM72V66441
Abstract: No abstract text available
Text: GM72V66441ET/ELT 4,194,304 W O R D x 4 B I T x 4 B A N K SYNCHRONOUS DYNAMIC RAM Description The GM72V66441ET/ELT is a synchronous dynamic random access memory comprised of 67,108,864 memory cells and logic including input and output circuits operating synchronously
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GM72V66441ET/ELT
GM72V66441ET/ELT
PC133/PC100/PC66
143MHz
133MHz
125MHz)
PC100
143/133/125/100MHz
GM72V66441
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2272 decoder
Abstract: GM72V66841ET EIAJ lcdd lpec1
Text: GM72V66841ET/ELT 2,097,152 WORD x 8 BIT x 4 BANK SYNCHRONOUS DYNAMIC RAM Description The GM72V66841ET/ELT is a synchronous dynamic random access memory comprised of 67,108,864 memory cells and logic including input and output circuits operating synchronously
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GM72V66841ET/ELT
GM72V66841ET/ELT
PC133/PC100/PC66
143MHz
133MHz
125MHz)
PC100
143/133/125/100MHz
2272 decoder
GM72V66841ET
EIAJ lcdd
lpec1
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HYB 39S128160CT-7
Abstract: HYB 39S128800CT-7 HYB 39S128160CT-7.5
Text: HYB 39S128400/800/160CT L 128-MBit Synchronous DRAM 128-MBit Synchronous DRAM • Multiple Burst Read with Single Write Operation • High Performance: -7 -7.5 -8 Units • Automatic and Controlled Precharge Command fCK 143 133 125 MHz • Data Mask for Read/Write Control (x4, x8)
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39S128400/800/160CT
128-MBit
P-TSOPII-54
400mil
PC100
P-TSOPII-54
GPX09039
HYB 39S128160CT-7
HYB 39S128800CT-7
HYB 39S128160CT-7.5
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Untitled
Abstract: No abstract text available
Text: HY57V281620HC 4 Banks x 2M x 16Bit Synchronous DRAM Preliminary DESCRIPTION The Hyundai HY57V281620HC is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V281620HC is organized as 4banks of 2,097,152x16
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HY57V281620HC
16Bit
HY57V281620HC
728bit
152x16
400mil
54pin
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Untitled
Abstract: No abstract text available
Text: HY57V28820HC 4Banks x 4M x 8Bit Synchronous DRAM DESCRIPTION The Hyundai HY57V28820HC is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V28820HC is organized as 4banks of
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HY57V28820HC
HY57V28820HC
728bit
304x8.
400mil
54pin
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Untitled
Abstract: No abstract text available
Text: HY57V28420HC 4Banks x 8M x 4Bit Synchronous DRAM DESCRIPTION The Hyundai HY57V28420HC is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V28420HC is organized as 4banks of
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HY57V28420HC
HY57V28420HC
728bit
608x4.
400mil
54pin
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39S256160T
Abstract: P-TSOPII-54
Text: HYB39S25640x/80x/16xT 256MBit Synchronous DRAM 256 MBit Synchronous DRAM Target Information Rev. 0.5 High Performance: -8 -10 Units fCK 125 100 MHz tCK3 8 10 ns tAC3 6 7 ns tAC2 6 8 ns • Multiple Burst Read with Single Write Operation • Automatic Command
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HYB39S25640x/80x/16xT
256MBit
P-TSOPII-54
400mil,
TSOPII-54
TSOP54-2
39S256160T
P-TSOPII-54
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W942516AH
Abstract: No abstract text available
Text: PRELIMINARY W942516AH 4M x 4 BANKS × 16 BIT DDR SDRAM GENERAL DESCRIPTION W942516AH is a CMOS Double Data Rate synchronous dynamic random access memory DDR SDRAM , organized as 4,194,304 words × 4 banks × 16 bits. Using pipelined architecture and 0.175
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W942516AH
W942516AH
DDR266/CL2
DDR200/CL2
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W942508AH
Abstract: W942516AH
Text: PRELIMINARY W942508AH 8M x 4 BANKS × 8 BIT DDR SDRAM GENERAL DESCRIPTION W942508AH is a CMOS Double Data Rate synchronous dynamic random access memory DDR SDRAM , organized as 8,388,608 words × 4 banks × 8 bits. Using pipelined architecture and 0.175 µm
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W942508AH
W942508AH
DDR266/CL2
DDR200/CL2
W942516AH
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39S256160DT-7
Abstract: HYB 39S256160DT-7.5 PC100-222 PC133-222 P-TSOPII-54 P-TSOP-54-2
Text: HYB39S256400/800/160DT L /DC(L) 256MBit Synchronous DRAM 256 MBit Synchronous DRAM • High Performance: -6 -7 -7.5 -8 Units • Data Mask for Read / Write control (x4, x8) • Data Mask for byte control (x16) • Auto Refresh (CBR) and Self Refresh fCK 166
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HYB39S256400/800/160DT
256MBit
P-TSOPII-54
400mil
P-TSOPII-54
GPX09039
TFBGA-54
39S256160DT-7
HYB 39S256160DT-7.5
PC100-222
PC133-222
P-TSOP-54-2
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MARKING CAW
Abstract: P-TSOPII-54
Text: HYB39S256400/800/160CT L 256MBit Synchronous DRAM 256 MBit Synchronous DRAM • High Performance: -7.5 -8 -8A Units fCK 133 125 125 MHz tCK3 7.5 8 8 ns tAC3 5.4 6 6 ns tCK2 10 10 12 ns tAC2 6 6 6 ns • Fully Synchronous to Positive Clock Edge • 0 to 70 °C operating temperature
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HYB39S256400/800/160CT
256MBit
P-TSOPII-54
400mil
PC133
PC100
SPT03933
MARKING CAW
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W941232AD
Abstract: No abstract text available
Text: W941232AD 1M x 4 BANKS × 32 BIT DDR SDRAM 1. GENERAL DESCRIPTION W941232AD is a CMOS Double Data Rate synchronous dynamic random access memory DDR SDRAM , organized as 1,048,576 words × 4 banks × 32 bits. Using pipelined architecture and 0.175 µm process technology, W941232AD delivers a data bandwidth of up to 800M words per second (-5).
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W941232AD
W941232AD
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Hitachi DSA00276
Abstract: No abstract text available
Text: HM5257165B-75/A6 HM5257805B-75/A6 HM5257405B-75/A6 512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword x 16-bit × 4-bank/16-Mword × 8-bit × 4-bank /32-Mword × 4-bit × 4-bank PC/133, PC/100 SDRAM ADE-203-1237A Z Rev. 1.0 Dec. 11, 2000 Description The Hitachi HM5257165B is a 512-Mbit SDRAM organized as 8388608-word × 16-bit × 4 bank. The
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HM5257165B-75/A6
HM5257805B-75/A6
HM5257405B-75/A6
Hz/100
16-bit
4-bank/16-Mword
/32-Mword
PC/133,
PC/100
ADE-203-1237A
Hitachi DSA00276
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Untitled
Abstract: No abstract text available
Text: HM5259165B-75/A6 HM5259805B-75/A6 HM5259405B-75/A6 512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword x 16-bit × 4-bank/16-Mword × 8-bit × 4-bank /32-Mword × 4-bit × 4-bank PC/133, PC/100 SDRAM E0118H10 Ver. 1.0 Apr. 6, 2001 Description The HM5259165B is a 512-Mbit SDRAM organized as 8388608-word × 16-bit × 4 bank. The HM5259805B
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HM5259165B-75/A6
HM5259805B-75/A6
HM5259405B-75/A6
Hz/100
16-bit
4-bank/16-Mword
/32-Mword
PC/133,
PC/100
E0118H10
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Untitled
Abstract: No abstract text available
Text: HM5257165B-75/A6 HM5257805B-75/A6 HM5257405B-75/A6 512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword x 16-bit × 4-bank/16-Mword × 8-bit × 4-bank /32-Mword × 4-bit × 4-bank PC/133, PC/100 SDRAM E0081H10 1st edition (Previous ADE-203-1237A (Z) Jan. 31, 2001
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HM5257165B-75/A6
HM5257805B-75/A6
HM5257405B-75/A6
Hz/100
16-bit
4-bank/16-Mword
/32-Mword
PC/133,
PC/100
E0081H10
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Hitachi DSA00164
Abstract: No abstract text available
Text: HM5251165B-75/A6/B6 HM5251805B-75/A6/B6 HM5251405B-75/A6/B6 512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword x 16-bit × 4-bank/16-Mword × 8-bit × 4-bank /32-Mword × 4-bit × 4-bank PC/133, PC/100 SDRAM ADE-203-1095 Z Preliminary Rev. 0.0 Sep. 1, 1999
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HM5251165B-75/A6/B6
HM5251805B-75/A6/B6
HM5251405B-75/A6/B6
Hz/100
16-bit
4-bank/16-Mword
/32-Mword
PC/133,
PC/100
ADE-203-1095
Hitachi DSA00164
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PC100-322-620
Abstract: 39S256 PC133 registered reference design HYB 39S256400CT-7.5 PC-100-322-620
Text: HYB39S256400/800/160CT L 256MBit Synchronous DRAM 256 MBit Synchronous DRAM • High Performance: -7.5 -8 -8A Units fCK 133 125 125 MHz tCK3 7.5 8 8 ns tAC3 5.4 6 6 ns tCK2 10 10 12 ns tAC2 6 6 6 ns • Fully Synchronous to Positive Clock Edge • 0 to 70 °C operating temperature
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HYB39S256400/800/160CT
256MBit
P-TSOPII-54
400mil
PC133
PC100
SPT03933
PC100-322-620
39S256
PC133 registered reference design
HYB 39S256400CT-7.5
PC-100-322-620
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39S256160T
Abstract: PC100-322-620 MARKING AX5 SMD MARKING T20
Text: HYB 39S256400/800/160T 256-MBit Synchronous DRAM 256-MBit Synchronous DRAM • Multiple Burst Read with Single Write Operation • High Performance: • Automatic and Controlled Precharge Command -7.5 -8 -8A -8B Units fCK 133 125 125 100 MHz tCK3 7.5 8 8 10
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39S256400/800/160T
256-MBit
SPT03933
39S256160T
PC100-322-620
MARKING AX5
SMD MARKING T20
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Untitled
Abstract: No abstract text available
Text: HYB 39S128400/800/160CT L 128-MBit Synchronous DRAM 128-MBit Synchronous DRAM • Multiple Burst Read with Single Write Operation • High Performance: -7 -7.5 -8 Units • Automatic and Controlled Precharge Command fCK 143 133 125 MHz • Data Mask for Read/Write Control (x4, x8)
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39S128400/800/160CT
128-MBit
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"sense amplifier" voltage control current precharge memory
Abstract: No abstract text available
Text: Application 2. Dynamic RAM DRAM 2.1 Features of DRAM DRAM has a simple two-element memory structure, consisting o f a single transistor and a single capacitor. Due to this feature, DRAM is suitable for a higher degree of chip integration and can implement low-price
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25MHz)
40MHz)
15nsi
66MHz)
"sense amplifier" voltage control current precharge memory
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