74HC112PW,112 datasheet
by NXP Semiconductors
- dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger ; F<sub>max</sub>: 66 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 17@5V ns; Voltage: 2.0-6.0 V; Package: SOT403-1 (TSSOP16); Container: Tube
- Original
- Yes
- Unknown
- Transferred
-
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