74HC112PW-T Search Results
74HC112PW-T Result Highlights (2)
Part | ECAD Model | Manufacturer | Description | Download | Buy |
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CD74HC112PWR |
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High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset 16-TSSOP -55 to 125 | |||
CD74HC112PWRE4 |
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High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset 16-TSSOP -55 to 125 |
74HC112PW-T Price and Stock
Texas Instruments CD74HC112PWTIC FF JK TYPE DUAL 1BIT 16TSSOP |
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Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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CD74HC112PWT | Digi-Reel | 698 | 1 |
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Buy Now | |||||
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CD74HC112PWT | 1,011 |
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Get Quote | |||||||
Texas Instruments CD74HC112PWRE4Flip Flops Hi-Sp CMOS Dual Neg J-K-Type Flip-Flop |
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Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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CD74HC112PWRE4 | 1,908 |
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Buy Now | |||||||
Texas Instruments CD74HC112PWRFlip Flops Dual Neg Edge Trig |
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Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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CD74HC112PWR | 1,878 |
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Buy Now |
74HC112PW-T Datasheets (2)
Part | ECAD Model | Manufacturer | Description | Curated | Datasheet Type | |
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74HC112PW-T |
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dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger ; Fmax: 66 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 17@5V ns; Voltage: 2.0-6.0 V | Original | |||
74HC112PW-T | Unknown | Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. | Historical |