LH75401
Abstract: LH75401N0Q100C0 LH75411 LH75411N0Q100C0 LQFP144
Text: LH75401/LH75411 System-on-Chip Preliminary data sheet DESCRIPTION • JTAG Debug Interface and Boundary Scan The NXP BlueStreak LH75401/LH75411 family consists of two low-cost 16/32-bit System-on-Chip SoC devices. • Single 3.3 V Supply • LH75401 — contains the superset of features.
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LH75401/LH75411
LH75401/LH75411
16/32-bit
LH75401
144-pin
LH75411
LH75401,
LH75401
12-bit
12-bit
LH75401N0Q100C0
LH75411N0Q100C0
LQFP144
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16F NEC
Abstract: caffeine iso7816 sim Marking DEot PCMCIA SRAM Card serial flash 256Mb fast erase spi ibm ps2 SMC SD MMC card reader Basic ARM 9tdmi block diagram cache port read ARM9T
Text: LH7A405 Advance Data Sheet FEATURES • ARM922T Core: – 32-bit ARM9TDMI™ RISC Core 200 MHz – 16KB Cache: 8KB Instruction Cache and 8KB Data Cache – MMU (Windows CE™ Enabled) 32-Bit System-on-Chip • Synchronous Serial Port (SSP) – Motorola SPI™
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LH7A405
ARM922TTM
32-bit
16C550-like
11/SD
SMA02004
16F NEC
caffeine
iso7816 sim
Marking DEot
PCMCIA SRAM Card
serial flash 256Mb fast erase spi
ibm ps2
SMC SD MMC card reader
Basic ARM 9tdmi block diagram
cache port read ARM9T
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Untitled
Abstract: No abstract text available
Text: LH79520 System-on-Chip Preliminary data sheet FEATURES • Flexible, Programmable Memory Interface – SDRAM Interface – 15-bit External Address Bus – 32-bit External Data Bus – Two Segments 128 MB each – SRAM/Flash/ROM Interface – 26-bit External Address Bus
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LH79520
15-bit
32-bit
26-bit
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Basic ARM 9tdmi block diagram
Abstract: AMBA AHB bus protocol LCD architecture ARM922T ISO7816 LH7A404 AA15 AC97 SMC SD MMC card reader LH7A404-28
Text: LH7A404 Advance Data Sheet FEATURES • ARM922T Core: – 32-bit ARM9TDMI™ RISC Core 200 MHz – 16KB Cache: 8KB Instruction Cache and 8KB Data Cache – MMU (Windows CE™ Enabled) • 80KB On-Chip Memory • Vectored Interrupt Controller • External Bus Interface
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LH7A404
ARM922TTM
32-bit
ISO7816)
SMA02004
Basic ARM 9tdmi block diagram
AMBA AHB bus protocol
LCD architecture
ARM922T
ISO7816
LH7A404
AA15
AC97
SMC SD MMC card reader
LH7A404-28
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Untitled
Abstract: No abstract text available
Text: IMPORTANT NOTICE Dear customer, As from June 1st, 2007 NXP Semiconductors has acquired the LH7xxx ARM Microcontrollers from Sharp Microelectronics. The following changes are applicable to the attached data sheet. In data sheets where the previous Sharp or Sharp Corporation references remain, please use the new
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Untitled
Abstract: No abstract text available
Text: LH7A400 32-Bit System-on-Chip Product data sheet FEATURES • Three Programmable Timers • 32-bit ARM9TDMI RISC Core – 16 kB Cache: 8 kB Instruction and 8 kB Data – MMU Windows CE™ Enabled – Up to 250 MHz; see Table 1 for options • Three UARTs
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LH7A400
32-Bit
ISO7816)
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95mV
Abstract: No abstract text available
Text: LH7A404 32-Bit System-on-Chip Preliminary Data Sheet FEATURES • PS/2 Keyboard/Mouse Interface KMI • ARM922T Core: – 32-bit ARM9TDMI™ RISC Core (200 MHz) – 16KB Cache: 8KB Instruction Cache and 8KB Data Cache – MMU (Windows CE™ Enabled) • Three Programmable Timers
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LH7A404
ARM922TTM
32-bit
10-bit
SMA02004
95mV
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20 pin lcd small panel
Abstract: slc 500 circuit diagram
Text: LH79524/LH79525 A.0 System-on-Chip Preliminary Data Sheet FEATURES • Highly Integrated System-on-Chip • High Performance: 76.205 MHz CPU Speed, 50.803 MHz maximum AHB clock (HCLK) • 32-bit ARM720T RISC Core – LH79524: 32-bit External Data Bus
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LH79524/LH79525
32-bit
ARM720TTM
LH79524:
LH79525:
16-bit
LH79524)
20 pin lcd small panel
slc 500 circuit diagram
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schematic OF IR TOUCH screen
Abstract: LH7A404-N0E-092-xx
Text: LH7A404 32-Bit System-on-Chip Data Sheet FEATURES • Three Programmable Timers • 32-bit ARM9TDMI RISC Core – 16KB Cache: 8KB Instruction and 8KB Data Cache – MMU Windows CE™ Enabled – Up to 266 MHz; See Table 1 for speed/temp options • Three UARTs, one with Classic IrDA (115 kbit/s)
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LH7A404
32-bit
10-bit
SMA02004
schematic OF IR TOUCH screen
LH7A404-N0E-092-xx
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ph08
Abstract: No abstract text available
Text: LH7A400 32-Bit System-on-Chip Data Sheet FEATURES • Smart Card Interface ISO7816 • 32-bit ARM9TDMI RISC Core – 16KB Cache: 8KB Instruction and 8KB Data – MMU (Windows CE™ Enabled) – Up to o 250 MHz; see Table 1 for options • Two DC-to-DC Converters
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LH7A400
32-bit
SMA01012
ph08
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china mobile phone circuit diagram T20
Abstract: No abstract text available
Text: LH7A404 32-Bit System-on-Chip Data Sheet FEATURES • 32-bit ARM9TDMI RISC Core – 16KB Cache: 8KB Instruction and 8KB Data Cache – MMU Windows CE™ Enabled – Up to 266 MHz; See Table 1 for speed/temp options • 80KB On-Chip Static RAM • Vectored Interrupt Controller
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LH7A404
32-bit
10-bit
SMA02004
china mobile phone circuit diagram T20
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Marking code PL6
Abstract: LH79524
Text: LH79524/LH79525 A.1 System-on-Chip Data Sheet FEATURES • I2C Module • Highly Integrated System-on-Chip • Integrated Codec Interface Support Features (I2S) • High Performance: 76.205 MHz CPU Speed, 50.803 MHz maximum AHB clock (HCLK) • Watchdog Timer
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LH79524/LH79525
32-bit
ARM720TTM
LH79524:
LH79525:
16-bit
LH79524)
Marking code PL6
LH79524
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Untitled
Abstract: No abstract text available
Text: LH79520 System-on-Chip Data Sheet FEATURES • 64 Programmable General Purpose I/O Signals – Multiplexed with Peripheral I/O Signals • Programmable Color LCD Controller – Up to 800 x 600 Resolution – Supports STN, Color STN, AD-TFT, TFT – Supports 15 Shades of Gray
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LH79520
ARM720TTM
32-bit
15-bit
128MB
26-bit
SMA00067
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Untitled
Abstract: No abstract text available
Text: LH79520 System-on-Chip Preliminary Data Sheet FEATURES • 64 Programmable General Purpose I/O Signals – Multiplexed with Peripheral I/O Signals • Highly Integrated System-on-Chip • Programmable Color LCD Controller – Up to 800 x 600 Resolution – Supports STN, Color STN, HR-TFT, TFT
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LH79520
ARM720TTM
32-bit
15-bit
128MB
26-bit
SMA00067
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ARM7 interfacing notes to LCD
Abstract: LH75401 LH75401N0Q100C0 LH75411 LH75411N0Q100C0 LQFP144
Text: LH75401/LH75411 System-on-Chip Product data sheet DESCRIPTION • JTAG Debug Interface and Boundary Scan The NXP BlueStreak LH75401/LH75411 family consists of two low-cost 16/32-bit System-on-Chip SoC devices. • Single 3.3 V Supply • LH75401 — contains the superset of features.
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LH75401/LH75411
LH75401/LH75411
16/32-bit
LH75401
144-pin
LH75411
LH75401,
LH75401
12-bit
12-bit
ARM7 interfacing notes to LCD
LH75401N0Q100C0
LH75411N0Q100C0
LQFP144
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Texas Instruments Power Reference Design for Intel Core i7
Abstract: ARM720T LH79524 LH79524N0F100A0 LH79524N0F100A1 LH79525 LH79525N0Q100A0 LH79525N0Q100A1 XTAL32OUT
Text: LH79524/LH79525 A.1 System-on-Chip Product data sheet FEATURES • I2C Module • Highly Integrated System-on-Chip • Integrated Codec Interface Support Features (I2S) • High Performance: 76.205 MHz CPU Speed, 50.803 MHz maximum AHB clock (HCLK) • Watchdog Timer
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LH79524/LH79525
32-bit
ARM720TTM
LH79524:
LH79525:
16-bit
LH79524)
Texas Instruments Power Reference Design for Intel Core i7
ARM720T
LH79524
LH79524N0F100A0
LH79524N0F100A1
LH79525
LH79525N0Q100A0
LH79525N0Q100A1
XTAL32OUT
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mtron
Abstract: ARM720T LH79520 LH79520N0Q000B1 LQFP176
Text: LH79520 System-on-Chip Preliminary data sheet FEATURES • Flexible, Programmable Memory Interface – SDRAM Interface – 15-bit External Address Bus – 32-bit External Data Bus – Two Segments 128 MB each – SRAM/Flash/ROM Interface – 26-bit External Address Bus
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LH79520
15-bit
32-bit
26-bit
mtron
ARM720T
LH79520
LH79520N0Q000B1
LQFP176
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ARM720T
Abstract: LH79524 LH79524N0F100A0 LH79524N0F100A1 LH79525 LH79525N0Q100A0 LH79525N0Q100A1 pk7 ur A4T10
Text: LH79524/LH79525 A.1 System-on-Chip Preliminary data sheet FEATURES • I2C Module • Highly Integrated System-on-Chip • Integrated Codec Interface Support Features (I2S) • High Performance: 76.205 MHz CPU Speed, 50.803 MHz maximum AHB clock (HCLK) • Watchdog Timer
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LH79524/LH79525
32-bit
ARM720TTM
LH79524:
LH79525:
16-bit
LH79524)
ARM720T
LH79524
LH79524N0F100A0
LH79524N0F100A1
LH79525
LH79525N0Q100A0
LH79525N0Q100A1
pk7 ur
A4T10
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LH75401
Abstract: Bosch PE6 LH75400 LH75410 LH75411 ARM7 interfacing notes to LCD XTAL32OUT 82510 uart
Text: LH75400/01/10/11 System-on-Chip Data Sheet DESCRIPTION • JTAG Debug Interface and Boundary Scan The SHARP BlueStreak LH75400/01/10/11 family consists of four low-cost 16/32-bit System-on-Chip SoC devices. • Single 3.3 V Supply • LH75401 — contains the superset of features.
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LH75400/01/10/11
LH75400/01/10/11
16/32-bit
LH75401
144-pin
LH75411
LH75401,
LH75400
LH75410
Bosch PE6
ARM7 interfacing notes to LCD
XTAL32OUT
82510 uart
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16C550
Abstract: ARM720T LH79520 LHF32J06 D2259 LH7952
Text: LH79520 Universal Microcontroller Preliminary User’s Guide 11/5/02 Content Revisions This document contains the following changes to content, causing it to differ from previous versions. Table 1. Record of Revisions DATE 11-15-02 PAGE NO. SECTION, TABLE,
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LH79520
16C550
ARM720T
LH79520
LHF32J06
D2259
LH7952
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LH7A404
Abstract: HT 25-19 transistor AC97 ARM922T LCD interface WITH ARM transistor k 2628 2G1 SMC SD MMC card reader marking a21c sdmc 1014 smart card contact
Text: LH7A404 Universal SOC Advance User’s Guide 6/13/03 This document is released as Beta-level documentation. SHARP reserves the right to change and amend this documentation as necessary to represent the final Production-level development of this device. Specifications are subject to change without notice.
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LH7A404
LH7A404
HT 25-19 transistor
AC97
ARM922T
LCD interface WITH ARM
transistor k 2628 2G1
SMC SD MMC card reader
marking a21c
sdmc 1014
smart card contact
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A2295
Abstract: capacitive touch controller IC LH7A404-6 AC97 ARM922T ISO7816 LH7A404 sharp lcd panel pinout SMC SD MMC card reader schematic OF IR TOUCH screen
Text: LH7A404 32-Bit System-on-Chip Preliminary Data Sheet FEATURES • PS/2 Keyboard/Mouse Interface KMI • ARM922T Core: – 32-bit ARM9TDMI™ RISC Core (200 MHz) – 16KB Cache: 8KB Instruction Cache and 8KB Data Cache – MMU (Windows CE™ Enabled) • Three Programmable Timers
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LH7A404
32-Bit
ARM922TTM
ISO7816)
11/SD
SMA02004
A2295
capacitive touch controller IC
LH7A404-6
AC97
ARM922T
ISO7816
LH7A404
sharp lcd panel pinout
SMC SD MMC card reader
schematic OF IR TOUCH screen
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LH7A400
Abstract: AC97 ARM922T ISO7816
Text: LH7A400 32-Bit System-on-Chip Preliminary Data Sheet FEATURES • Three Programmable Timers • ARM922T Core: – 32-bit ARM9TDMI™ RISC Core – 16KB Cache: 8KB Instruction Cache and 8KB Data Cache – MMU Windows CE Enabled • Three UARTs – Classic IrDA (115 kbit/s)
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LH7A400
32-Bit
ARM922TTM
ISO7816)
SMA01012
LH7A400
AC97
ARM922T
ISO7816
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Untitled
Abstract: No abstract text available
Text: LH79524/LH79525 A.1 System-on-Chip Preliminary data sheet FEATURES • I2C Module • Highly Integrated System-on-Chip • Integrated Codec Interface Support Features (I2S) • High Performance: 76.205 MHz CPU Speed, 50.803 MHz maximum AHB clock (HCLK) • Watchdog Timer
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LH79524/LH79525
32-bit
ARM720Tâ
LH79524:
LH79525:
16-bit
LH79524)
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