XDATA30 Search Results

SuperSPARC

Abstract: Mbus master 250 slave circuit tmx390 STP1091-60
Contextual Info: S un M icroelectronics July 1997 Multi-Cache Controller DATA SHEET Integrated Cache Controller for SuperSPARC D e s c r ip t io n The STP1091 is a high-performance external cache controller for the STP1020 SuperSPARC and STP1021 (SuperSPARC-II) microprocessors. It is used when a large secondary cache or an interface to a non-MBus sys­

MT48LC8M16A2

Abstract: PC15 RTL8201BL header8 DB9_MALE AT45DB128
Contextual Info: Port C Pins assignment 104 PB22/SCK1 as UART1 RI Input 122 PB27/PCK0 as UART1 DTR (Output) ADDR12 not connected to U3,U4 ADDR13 connected to U3.A11,U4.A11 See Page 139 Man.rev.from 22-Aug-03 R11 10 C27 0.1uF R14 10 C30 0.1uF R18 10 C19 0.1uF VDDPLL PLLRCA

ARM10TDMI

Abstract: LOG rx2 1018 ahb fsm minFrameSize-160 0x85000000 S3C2500 book national semiconductor LOG TX2 1044 0xF001000
Contextual Info: 20-S3-C2500-052002 USER'S MANUAL S3C2500 32-Bit RISC Microprocessor Revision 0 S3C2500 Preliminary Spec 1 PRODUCT OVERVIEW PRODUCT OVERVIEW 1.1 OVERVIEW Samsung's S3C2500 16/32-bit RISC microcontroller is a cost-effective, high-performance microcontroller

sony rxd7

Contextual Info: S O N Y C XD1700 E thernet S w itch Features: ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ Fully Integrated Ethernet Switch On A Chip Twenty Four 10Base-X Ports, Two 10/100Base-X Ports All Ports can be either Full or Half Duplex Low Per-Port Cost

Contextual Info: STP1091 S un M ic r o e l e c t r o n ic s J u ly 1997 Multi-Cache Controller DATA SHEET Integrated Cache Controller for SuperSPARC D e s c r ip t io n The STP1091 is a high-perform ance external cache controller for the STP1020 SuperSPARC and STP1021

29f016a

Abstract: NC32 74HCT125 ADDR12 TG22-3506ND MDIO10 TP181 VSS198 ADDR15 1R58
Contextual Info: 5 4 3 2 1 +5V This document is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. U1 DS1813/TO92 +5V +5V 1 VCC 14 NC 4 7 GND OUT 11 GND OUT1 8

UDL42

Abstract: UDL45 UDL33 UDL44
Contextual Info: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT µPD66702, µPD66703 System-on-Chip Lite+ Extended ARM7TDMI-STM-based, Customizable Microcontroller 32-Bit RISC CPU Core DESCRIPTION System-on-Chip Lite+ is based on standard ASIC technology and consists of two blocks: an ARM7TDMI-S

Contextual Info: .6êë&èíìííý5,6&ý0,&52&21752// 5 352'8&7ý29(59,(: ýýýýýýýýýý3UHOLPLQDU\ý9(5ïýýíïê ýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýýý0DUFKïýýìäää

Contextual Info: Prelimina: SIARCTechnology STP1090A Business January Multi-Cache Controller ,TM DATA. SE ET Integrated Cache Controller for SuperSPARC D e s c r ip t io n The STP1090A is a high-perform ance external cache controller for the STP1020A SuperSPARC and STP1021 (SuperSPARC-II) microprocessors. It is used w hen a large secondary cache or an interface

S3C2500

Abstract: S3C2510 ARM10TDMI MCR 100-6 P 1037 fm receiver ic MRC D17 ARM9TDMI comparison between ARM7TDMI and ARM10TDMI highway speed checker IC data book free download
Contextual Info: 21-S3C2500B-032003 USER'S MANUAL S3C2500B 32-Bit RISC Microprocessor Revision 1 S3C2500B 32-BIT RISC MICROPROCESSOR USER'S MANUAL Revision 1 Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the

bdv 83 do

Abstract: CMOS-9HD A15647EE1V0DS00 ea-9hd
Contextual Info: Preliminary User’s Manual System-on-Chip Lite Gate Array with ARM7TDMI Subsystem, 32-Bit RISC CPU Core Hardware µPD65977S1-xxx-B6 Document No. A15402EE1V0UM00 Date Published August 2001  NEC Corporation 2001 Printed in Germany NOTES FOR CMOS DEVICES

STDM85

Abstract: KS32C5000AA hdlc KS32C5000A KS32C500
Contextual Info: 20.3-32-5000A Data Sheet KS32C5000A RISC Microcontroller Revision 0.1 KS32C5000A RISC MICROCONTROLLER DATA SHEET INTRODUCTION Samsung’s KS32C5000AA 16/32-bit RISC microcontroller is a cost-effective, high-performance microcontroller solution for Ethernet-based systems. The KS32C5000AA is designed as an integrated Ethernet controller for use in

schematic circuit adsl router part list

Abstract: 29e010 78R05 KS32C50100 SNDS100 78R33 MAX232 CPE 29e010 datasheet c-mac stp samsung ribbon
Contextual Info: Excellence in Low-Power The way MICOM/DSP should be KS32C5000 A /KS32C50100 32-bit RISC Microcontroller for Network Solution Mar. 1999 ELECTRONICS Contents n n n Network Protocol n What is Network ? n OSI Reference Model and TCP/IP n TCP/IP Networking Software & Basic Protocol

TMx390

Abstract: SuperSPARC STP1020 STP1021A MAD19 STP1091 ADDR02 Mbus master 250 slave circuit stp1090 imad-26
Contextual Info: STP1091.frm Page 97 Monday, August 25, 1997 3:08 PM STP1091 July 1997 Multi-Cache Controller DATA SHEET Integrated Cache Controller for SuperSPARC DESCRIPTION The STP1091 is a high-performance external cache controller for the STP1020 SuperSPARC and STP1021 (SuperSPARC-II) microprocessors. It is used when a large secondary cache or an interface to a non-MBus system is required.

stm 8309

Abstract: ARM10TDMI ARM9TDMI power supply SAMSUNG MONITOR str 8309 ARM v7 XXAB ccd diode datasheet ap6 comparison between ARM7TDMI and ARM10TDMI comparison between core performance of ARM7TDMI
Contextual Info: S3C2501X 32-BIT RISC MICROPROCESSOR USER'S MANUAL Revision 1 Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or

tmx390

Abstract: supersparc PM 438 BL capacitor 471 aj7 tmx390x55 tpvc01
Contextual Info: STP1091.frm Page 97 Monday, August 25, 1997 3:08 PM S un M ic r o e l e c t r o n ic s July 1997 Multi-Cache Controller DATA SHEET Integrated Cache Controller for SuperSPARC D e s c r ip t io n The STP1091 is a high-performance external cache controller for the STP1020 SuperSPARC and STP1021 (Super­

78R05

Abstract: schematic diagram tcon samsung smd code16 specification of Ic 8951 8951 INSTRUCTIONS SET smd cookbook NB b6 smd transistor csr schematic usb to spi SCR c106 PIN CONFIGURATION 8951 Microcontroller
Contextual Info: S5N8947 MCU for DSL USER’s MANUAL Oct 30, 2001 SAMSUNG Electronics Co., LTD. IMPORTANT NOTICE SAMSUNG reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest

S3C2510

Abstract: 733h S3C2510A MS 7541 MOTHERBOARD SERVICE MANUAL 21-S3-C2510-032003 MS 7541 ver 1.2 MOTHERBOARD SERVICE MANUAL MRC D17 ccd diode datasheet ap6 comparison between ARM7TDMI and ARM10TDMI ARM940T
Contextual Info: 21-S3-C2510-032003 USER'S MANUAL S3C2510A 32-Bit RISC Microprocessor Revision 1 S3C2510A 32-BIT RISC MICROPROCESSOR USER'S MANUAL Revision 1 Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the

A15647EE2V0DS00

Abstract: A15402EE1V0UM00 CMOS-9HD ea-9hd number of pins of ARM7 bv08
Contextual Info: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT µPD65977S1-xxx-B6 SYSTEM-ON-CHIP LITE GATE ARRAY WITH ARM7TDMI SUBSYSTEM HARDWARE DESCRIPTION The System-on-Chip Lite "SoCLite" is based on standard ASIC technology and consists of two blocks: an ARM7TDMI based subsystem and a sea-of-gates area. The ARM subsystem is fully designed and verified as a

STDM85

Abstract: hdlc netarm 40 0x9014
Contextual Info: 20.3-32-5000 Data Sheet KS32C5000 RISC Microcontroller Revision 0.3 KS32C5000 RISC MICROCONTROLLER DATA SHEET INTRODUCTION Samsung’s KS32C5000 16/32-bit RISC microcontroller is a cost-effective, high-performance microcontroller solution for Ethernet-based systems. The KS32C5000 is designed as an integrated Ethernet controller for use in

ks32c

Abstract: COK- 001
Contextual Info: 20.3-32-5000 Data Sheet KS32C5000 RISC Microcontroller Revision 0.3 KS32C5000 RISC MICROCONTROLLER DATA SHEET INTRODUCTION Samsung’s KS32C5000 16/32-bit RISC microcontroller is a cost-effective, high-performance microcontroller solution for Ethernet-based systems. The KS32C5000 is designed as an integrated Ethernet controller for use in

it6902

Abstract: MDC25 B241T micron dram code "Spanning Tree"
Contextual Info: C XD1700 S O N Y E thernet S w itch Features: ♦ Fully Integrated Ethernet Switch On A Chip ♦ Twenty Four 10Base-X Ports, Two 10/100Base-X Ports ♦ All Ports can be either Full or Half Duplex ♦ Low Per-Port Cost ♦ 1.28 Gbps Bus Bandwidth ♦ High Capacity Rx and Tx FIFOs and Tx Queue, which