W24C Search Results

W24C

Contextual Info: 24 Lead Cerpack NS Package Number W24C All dimensions are in inches millimeters LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL

54ACTQ657

Contextual Info: 54ACTQ657 Quiet Series Octal Bidirectional Transceiver with 8-Bit Parity Generator/Checker and TRI-STATE Outputs General Description Features The ACTQ657 contains eight non-inverting buffers with TRI-STATE outputs and an 8-bit parity generator/checker. Intended for bus oriented applications, the device combines

diode E0A

Abstract: 93L08 93L08DMQB 93L08FMQB C1995 J24A W24C
Contextual Info: 93L08 Dual 4-Bit Latch General Description The 93L08 is a dual 4-bit D-type latch designed for general purpose storage applications in digital systems Each latch contains both an active LOW Master Reset input and active LOW Enable inputs Connection Diagram

54F676DM

Abstract: 54F676FM 54F676SDM 74F676 74F676PC 74F676SC 74F676SPC N24A N24C
Contextual Info: 54F 74F676 16-Bit Serial Parallel-In Serial-Out Shift Register General Description Features The ’F676 contains 16 flip-flops with provision for synchronous parallel or serial entry and serial output When the Mode M input is HIGH information present on the parallel

National AN-64

Abstract: 54F544LM 54F544SDM 74F544 74F544MSA 74F544SC 74F544SPC N24C 54F544DM 54F544FM
Contextual Info: 54F 74F544 Octal Registered Transceiver General Description Features The ’F544 octal transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction Separate Latch Enable and Output Enable inputs are provided for each register to permit independent control of

AM248

Abstract: 54F825FM 54F825LM 54F825SDM 74F825 74F825SC 74F825SPC J24F M24B N24C
Contextual Info: 54F 74F825 8-Bit D-Type Flip-Flop General Description Features The ’F825 is an 8-bit buffered register It has Clock Enable and Clear features which are ideal for parity bus interfacing in high performance microprogramming systems Also included in the ’F825 are multiple enables that allow multiuser control of the interface

DS100233

Abstract: 54ACTQ543 54ACTQ543DMQB 54ACTQ543FMQB 54ACTQ543LMQB E28A J24A W24C actq543
Contextual Info: 54ACTQ543 Quiet Series Octal Registered Transceiver with TRI-STATE Outputs General Description Features The ACTQ543 is a non-inverting octal transceiver containing two sets of D-type registers for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent input and output control in either direction of data

F100K

Contextual Info: 100355 Low Power Quad Multiplexer/Latch General Description The 100355 contains four transparent latches, each of which can accept and store data from two sources. When both Enable En inputs are LOW, the data that appears at an output is controlled by the Select (Sn) inputs, as shown in the Operating Mode table. In addition to routing data from either D0 or

LVX4245

Abstract: 54LVX4245 54LVX4245J-QML 54LVX4245W-QML J24F W24C
Contextual Info: 54LVX4245 8-Bit Dual Supply Translating Transceiver with TRI-STATE Outputs General Description Features The LVX4245 is a dual-supply, 8-bit translating transceiver that is designed to interface between a 5V bus and a 3V bus in a mixed 3V/5V supply environment. The Transmit/Receive

54F657FM

Abstract: 54F657LM 54F657SDM 74F657 74F657SPC 75F657SC F245 F657 N24C
Contextual Info: 54F 74F657 Octal Bidirectional Transceiver with 8-Bit Parity Generator Checker and TRI-STATE Outputs General Description Features The ’F657 contains eight non-inverting buffers with TRI-STATE outputs and an 8-bit parity generator checker It is intended for bus-oriented applications The buffers have

LVXC3245

Abstract: W24A 54LVXC3245 54LVXC3245J-QML 54LVXC3245W-QML J24F
Contextual Info: 54LVXC3245 8-Bit Dual Supply Configurable Voltage Interface Transceiver with TRI-STATE Outputs General Description Features The LVXC3245 is a 24-pin dual-supply, 8-bit configurable voltage interface transceiver suited for real time configurable I/O applications. The VCCA pin accepts a 3V supply level.

Contextual Info: 54LVX3383 10-Bit Low Power Bus-Exchange Switch General Description Features The 54LVX3383 provides two sets of high-speed CMOS TTL-compatible bus switches. The low on resistance of the switch allows inputs to be connected to outputs without adding propagation delay or generating additional ground

Contextual Info: 100355 Low Power Quad Multiplexer/Latch General Description The 100355 contains four transparent latches, each of which can accept and store data from two sources. When both Enable En inputs are LOW, the data that appears at an output is controlled by the Select (Sn) inputs, as shown in the Operating Mode table. In addition to routing data from either D0 or

9581

Contextual Info: 54F 74F651  54F 74F652 Transceivers Registers General Description Features These devices consist of bus transceiver circuits with D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the input bus or from internal registers Data on the A or B bus will be

Contextual Info: 54LVXC4245 8-Bit Dual Supply Configurable Voltage Interface Transceiver with TRI-STATE Outputs General Description Features The LVXC4245 is a 24-pin dual-supply, 8-bit configurable voltage interface transceiver suited for real time configurable I/O applications. The VCCA pin accepts a 5V supply level.

LVXC32

Abstract: MARK* W24A
Contextual Info: 54LVXC3245 8-Bit Dual Supply Configurable Voltage Interface Transceiver with TRI-STATE Outputs General Description Features The LVXC3245 is a 24-pin dual-supply, 8-bit configurable voltage interface transceiver suited for real time configurable I/O applications. The VCCA pin accepts a 3V supply level.

54ABT543

Abstract: 54ABT543E-QML 54ABT543J-QML 54ABT543W-QML ABT543 E28A J24A W24C
Contextual Info: 54ABT543 Octal Registered Transceiver with TRI-STATE Outputs General Description The ’ABT543 octal transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are

Contextual Info: 54F 74F181 4-Bit Arithmetic Logic Unit General Description Features The ’F181 is a 4-bit Arithmetic logic Unit ALU which can perform all the possible 16 logic operations on two variables and a variety of arithmetic operations It is 40% faster than the Schottky ALU and only consumes 30% as much power

w24c

Contextual Info: June 1989 Semiconductor 93L08 Dual 4-Bit Latch General Description The 93L08 is a dual 4-bit D-type latch designed for general purpose storage applications in digital systems. Each latch contains both an active LOW Master Reset input and active LOW Enable inputs.

54F657FM

Abstract: 54F657SDM 74F657SPC 75F657SC F245 F657 J24F M24B N24C
Contextual Info: 0> Ul -s| N a t i o n a l Se mi c onduc t or 54F/74F657 Octal Bidirectional Transceiver with 8-Bit Parity Generator/Checker and TRI-STATE Outputs General Description Features The 'F657 contains eight non-inverting buffers with TRI-STATE® outputs and an 8-bit parity generator/checker.

Contextual Info: 54ACTQ543 54ACTQ543 Quiet Series Octal Registered Transceiver with TRI-STATE Outputs Literature Number: SNOS056 54ACTQ543 Quiet Series Octal Registered Transceiver with TRI-STATE Outputs General Description Features The ACTQ543 is a non-inverting octal transceiver containing

54LVX3383

Abstract: 54LVX3383J-QML 54LVX3383W-QML J24F W24C
Contextual Info: 54LVX3383 10-Bit Low Power Bus-Exchange Switch General Description Features The 54LVX3383 provides two sets of high-speed CMOS TTL-compatible bus switches. The low on resistance of the switch allows inputs to be connected to outputs without adding propagation delay or generating additional ground

9821

Abstract: MAX PLUS II free alu DM74LS181N CIRCUIT DIAGRAM CNA4 C1995 DM54LS181 DM54LS181J DM54LS181W DM74LS181 DM74LS181N
Contextual Info: DM54LS181 DM74LS181 4-Bit Arithmetic Logic Unit General Description Features The ’LS181 is a 4-bit Arithmetic Logic Unit ALU which can perform all the possible 16 logic operations on two variables and a variety of arithmetic operations Y Y Y Provides 16 arithmetic operations add subtract compare double plus twelve other arithmetic operations

74ACQ544

Abstract: 74ACTQ544 C1995
Contextual Info: 74ACQ544  54ACTQ 74ACTQ544 Quiet Series Octal Registered Transceiver with TRI-STATE Outputs General Description Features The ’ACQ ’ACTQ544 is an inverting octal transceiver containing two sets of D-type registers for temporary storage of data flowing in either direction Separate Latch Enable and