W18 CMS TRANSISTOR Search Results

8 pin diagram 393w

Abstract: RBDR OTB33LL A500K270 RAM256X9AA
Contextual Info: Preliminary v1.1 ProASIC 500K Family I/O Fe a t ur es an d B e ne f i ts • Mixed 2.5/3.3 Volt Support • 3.3V, 33 MHz PCI Compliance PCI Revision 2.2 • Individually Selectable 2.5V or 3.3V I/Os and Slew Rate High C apaci t y • 100,000 to 475,000 System Gates

TMX320TCI6614

Abstract: serial parallel transport stream 320TCI6614 smart data slicer 900-PIN msm 8625 wcdma rake receiver sprugy9 TMS320TCI6614
Contextual Info: TMS320TCI6614 Communications Infrastructure KeyStone SoC Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Contextual Info: v2.0 ProASIC 500K Family I/O Fe a t ur es an d B e ne f i ts • Mixed 2.5V/3.3V Support with Individually-Selectable Voltage and Slew Rate • 3.3V, PCI Compliance PCI Revision 2.2 High C apaci t y • 100,000 to 475,000 System Gates • 14k to 63k Bits of Two-Port SRAM

Contextual Info: TMS320TCI6612 Communications Infrastructure KeyStone SoC Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

model RB-30 S PT 100

Abstract: RAM256X9SST Libero FIFO256X9SSRP GL25 A500K050 A500K130 A500K180 A500K270 OB-25
Contextual Info: v3.0 ProASIC 500K Family I/O Fe a t ur es an d B e ne f i ts • Mixed 2.5V/3.3V Support with Individually-Selectable Voltage and Slew Rate • 3.3V, PCI Compliance PCI Revision 2.2 High C apaci t y • 100,000 to 475,000 System Gates • 14k to 63k Bits of Two-Port SRAM

Contextual Info: TCI6630K2L SPRS893B—June 2013—Revised March 2014 Multicore DSP+ARM KeyStone II System-on-Chip SoC 1 TCI6630K2L Features and Description 1.1 Features • ARM CorePac – Two ARM Cortex -A15 MPCore™ Processors at Up To 1.4 GHz – 1MB L2 Cache Memory Shared by Two ARM Cores

TCI6614

Abstract: sprugy9 TMS320TCI6614 SoC ARM cortex 64bit Hardware Manual
Contextual Info: TMS320TCI6614 Communications Infrastructure KeyStone SoC Data Manual ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. Literature Number: SPRS671A

A500K050

Abstract: A500K130 A500K180 A500K270 IOAD16 C24IO
Contextual Info: Discontinued – v3.0 ProASIC 500K Family F ea t u re s an d B e n e fi t s I/O • Mixed 2.5V/3.3V Support with Individually-Selectable Voltage and Slew Rate • 3.3V, PCI Compliance PCI Revision 2.2 H ig h C a p ac it y • 100,000 to 475,000 System Gates

A500K270

Abstract: DD 127 D transistor
Contextual Info: Advanced v.4 ProASIC 500K Family I/O Fe a t ur es an d B e ne f i ts • Mixed 2.5/3.3 Volt Support • 3.3V, 33 MHz PCI Compliance PCI Revision 2.2 • Individually Selectable 2.5V or 3.3V I/Os and Slew Rate High C apaci t y • 98,000 to 473,000 System Gates

msm 8625

Abstract: TCI6614
Contextual Info: TMS320TCI6612 Communications Infrastructure KeyStone SoC Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

msm 8625

Abstract: TCI6612 900-PIN TMS 1000 MP 3310 Texas
Contextual Info: TMS320TCI6612 Communications Infrastructure KeyStone SoC Data Manual ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. Literature Number: SPRS784B

TMS320TCI6614

Abstract: TCI6614 msm 8625
Contextual Info: TMS320TCI6614 Communications Infrastructure KeyStone SoC Data Manual ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. Literature Number: SPRS671B

Contextual Info: TMS320TCI6612 Communications Infrastructure KeyStone SoC Data Manual ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. Literature Number: SPRS784B

Contextual Info: Product Folder Sample & Buy Technical Documents Tools & Software Support & Community TCI6630K2L SPRS893E – MAY 2013 – REVISED JANUARY 2015 TCI6630K2L Multicore DSP+ARM KeyStone II System-on-Chip SoC 1 TCI6630K2L Features and Description 1.1 Features

apa1000

Contextual Info: v4.1 ProASICPLUS TM Flash Family FPGAs Features and Benefits High Capacity Commercial and Industrial • • • 75,000 to 1 Million System Gates 27 k to 198 kbits of Two-Port SRAM 66 to 712 User I/Os Military and Mil-Std 883B • • • 300, 000 to 1 million System Gates

ACTEL proASIC PLUS

Abstract: RAM256X9SST APA150 FIFO256X9SST ACTEL proASIC PLUS APA450
Contextual Info: v2.0  ProASICPLUS Flash Family FPGAs F ea t u re s an d B e n e fi t s • 100% Routability and Utilization H ig h C a p ac it y I/O • 75,000 to 1 million System Gates • 27k to 198kbits of Two-Port SRAM • 66 to 712 User I/Os Re pr og ra mm a b le Fl as h T ec h no lo g y

schematic diagram online UPS for high frequency

Abstract: ag19
Contextual Info: v3.3 ProASICPLUS TM Flash Family FPGAs Features and Benefits • • High Capacity I/O • • • • • 75,000 to 1 million System Gates 27k to 198kbits of Two-Port SRAM 66 to 712 User I/Os Reprogrammable Flash Technology • • • • 0.22µ 4LM Flash-based CMOS Process

APA750

Abstract: GL25 4kx8 sram
Contextual Info: v3 .4 PLUS ProASIC TM Flash Family FPGAs Features and Benefits • • High Capacity I/O • • • • • 75,000 to 1 million System Gates 27k to 198kbits of Two-Port SRAM 66 to 712 User I/Os Reprogrammable Flash Technology • • • • 0.22µ 4LM Flash-based CMOS Process

Contextual Info: v2.0  ProASICPLUS Flash Family FPGAs F ea t u re s an d B e n e fi t s • 100% Routability and Utilization H ig h C a p ac it y I/O • 75,000 to 1 million System Gates • 27k to 198kbits of Two-Port SRAM • 66 to 712 User I/Os Re pr og ra mm a b le Fl as h T ec h no lo g y

Contextual Info: v4.1 ProASICPLUS TM Flash Family FPGAs Features and Benefits High Capacity Commercial and Industrial • • • 75,000 to 1 Million System Gates 27 k to 198 kbits of Two-Port SRAM 66 to 712 User I/Os Military and Mil-Std 883B • • • 300, 000 to 1 million System Gates

ACTEL CCGA 624 mechanical

Abstract: APA075
Contextual Info: v4.0 ProASICPLUS TM Flash Family FPGAs Features and Benefits High Capacity Commercial and Industrial • • • 75,000 to 1 Million System Gates 27 k to 198 kbits of Two-Port SRAM 66 to 712 User I/Os Military and Mil-Std 883B • • • 300, 000 to 1 million System Gates

p21 transistor

Abstract: PECLR ACTEL proASIC PLUS APA450
Contextual Info: v2.0  ProASICPLUS Flash Family FPGAs F ea t u re s an d B e n e fi t s • 100% Routability and Utilization H ig h C a p ac it y I/O • 75,000 to 1 million System Gates • 27k to 198kbits of Two-Port SRAM • 66 to 712 User I/Os Re pr og ra mm a b le Fl as h T ec h no lo g y

ACTEL proASIC PLUS

Abstract: ACTEL proASIC PLUS APA450 ProASIC PLUS v0.1
Contextual Info: v2.0  ProASICPLUS Flash Family FPGAs F ea t u re s an d B e n e fi t s • 100% Routability and Utilization H ig h C a p ac it y I/O • 75,000 to 1 million System Gates • 27k to 198kbits of Two-Port SRAM • 66 to 712 User I/Os Re pr og ra mm a b le Fl as h T ec h no lo g y

capacitor 104 m30

Contextual Info: v3.5 ProASICPLUS TM Flash Family FPGAs Features and Benefits • • High Capacity I/O • • • • • 75,000 to 1 Million System Gates 27k to 198kbits of Two-Port SRAM 66 to 712 User I/Os Reprogrammable Flash Technology • • • • 0.22µ 4LM Flash-Based CMOS Process