Untitled
Abstract: No abstract text available
Text: g Military 54F02 MOTOROLA Quad 2-Input NOR Gate MPO ELECTRICALLY TESTED PER: MIL-M-38510/33301 lllllll LOGIC DIAGRAM Vqc Y4 B4 A4 Y3 B3 A3 AVAILABLE AS: 1) JAN: JM38510/33301BXA 2) SMD: N/A 3)883: 54F02/BXAJC X = CASE OUTLINE AS FOLLOWS: PACKAGE: CERDIP: C
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54F02
MIL-M-38510/33301
JM38510/33301BXA
54F02/BXAJC
56A-02
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Untitled
Abstract: No abstract text available
Text: g MOTOROLA M ilitary 54F11 Triple 3-Input AND Gate MP0 ELECTRICALLY TESTED PER: MIL-M-38510/34002 « ///// LOGIC DIAGRAM Vqc C1 Y1 C3 B3 A3 Y3 nri frri [TT] rrn H nn it i AVAILABLE AS: 1) JAN: JM38510/34002BXA 2) SMD: N/A 3 )8 8 3 : 54F11/BXAJC X = CASE OUTLINE AS FOLLOWS:
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MIL-M-38510/34002
54F11
JM38510/34002BXA
54F11/BXAJC
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DM54S189AJ
Abstract: DM54S189J DM74S189 DM74S289 S189 DM74S189N DM54S189
Text: DM54S189/DM74S189/DM54S189A/DM7 4S189 A National Ju i Semiconductor DM54S189/DM74S189 64-Bit 16 x 4 TRI-STATE RAM DM54S189A/DM74S189A High Speed 64-Bit TRI-STATE RAM General Description available at the outputs when the read/write input is high and the chip-enable is low. When the chip-enable is high,
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DM54S189/DM74S189
64-Bit
DM54S189A/DM74S189A
64-Bit
DM74S
TL/D/9232-5
54S189(
M74S189
DM54S189AJ
DM54S189J
DM74S189
DM74S289
S189
DM74S189N
DM54S189
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54LS132
Abstract: 1N3064 1-INPUT NAND SCHMITT TRIGGER 54LS132 MOTOROLA
Text: M Military 54LS132 M O TO RO LA Quad 2-Input Schmitt-TVigger Positive NAND Gate MPO ELE C TR IC A LLY TESTED PER: M IL-M -38510/31303 H U M The 54LS132 contains four 2-input NAND Gates which accept standard TTL input signals and provide standard TTL output levels. They
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MIL-M-38510/31303
54LS132
1N3064
1-INPUT NAND SCHMITT TRIGGER
54LS132 MOTOROLA
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Untitled
Abstract: No abstract text available
Text: NATIONAL SEMICOND -CLOGICJ IDE D | bSD1155 0DbSS71 3 | s 5E oi National Semiconductor 3 ä MM54HCT00/MM74HCT00 Quad 2 Input NAND Gate s General Description X o H o o The MM54HCT00/MM74HCT00 are NAND gates fabricated using advanced silicon-gate CMOS technology which pro
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bSD1155
0DbSS71
MM54HCT00/MM74HCT00
DM54LS/74LS
MM54HCT/MM74HCT
cHCT00/MM74HCT00
--12mW/
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398B
Abstract: J-131 DM54LS86J DM54LS86W DM74LS86 DM74LS86M DM74LS86N J14A M14A N14A
Text: S E M IC O N D U C T O R tm DM74LS86 Quad 2-Input Exclusive-OR Gates General Description This device contains four independent gates each of which perform s the logic exclusive-O R function. Connection Diagram D ual-ln-Line Package Vcc | 14 B4 A4 13 Y4 12
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DM74LS86
DS006380-1
DM54LS86J,
DM54LS86W,
DM74LS86M
DM74LS86N
DS006380
14-Lead
398B
J-131
DM54LS86J
DM54LS86W
DM74LS86
J14A
M14A
N14A
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ic 747 cn
Abstract: 74als747 LS747
Text: SN 54A LS746, SN 54A LS747, SN 74A LS746, SN 74A LS747 OCTAL BUFFERS AND LINE DRIVERS WITH INPUT PULL-UP RESISTORS AU G U S T 1 9 8 4 - • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers REVISED M A Y 1 9 8 6 S N 5 4 A L S 7 4 6 , S N 5 4 A L S 7 4 7 . . . J PACKAGE
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LS746,
LS747,
LS747
300-mil
SN74ALS747
ic 747 cn
74als747
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VHC126
Abstract: No abstract text available
Text: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Quad Bus Buffer MC74VHC126 w ith 3-S ta te Control Inputs The MC74VHC126 is a high speed CMOS quad bus buffer fabricated with silicon gate CM OS technology. It achieves noninverting high speed operation similar to equivalent Bipolar Schottky TTL while maintaining
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MC74VHC126
DL203
MC74VHC126
VHC126
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54LS32
Abstract: No abstract text available
Text: g M ilitary 54LS32 MOTOROLA Quad 2-Input OR Gate MP0 ELECTRICALLY TESTED PER: MIL-M-38510/30501 LOGIC DIAGRAM Vqc ra B4 A4 Y4 r ii füi [Tn B3 A3 m in t Y3 Roí nn m AVAILABLE AS: 1) JAN: JM38510/30501BXA 2) SMD: N/A 3)883: 54LS32/BXAJC X = CASE OUTLINE AS FOLLOWS:
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54LS32
MIL-M-38510/30501
JM38510/30501BXA
54LS32/BXAJC
56A-02
1N3064
54LS32
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Untitled
Abstract: No abstract text available
Text: MOTOROLA M ilita ry 54F 3 2 Quad 2-In p u t OR G ate MPO ELECTRICALLY TESTED PER: MIL-M-38510/33501 HUM LOGIC DIAGRAM VqC A4 B4 Y4 B3 A3 Y3 AVAILABLE AS: 1 JAN: JM38510/33501BXA 2) SMD: N/A 3) 883: 54F32/BXAJC X = CASE OUTLINE AS FOLLOWS: PACKAGE: CEROIP: C
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MIL-M-38510/33501
JM38510/33501BXA
54F32/BXAJC
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Untitled
Abstract: No abstract text available
Text: d t M ULTILEVEL PIPELINE REGISTERS IDT29FCT520A/B !D T 29FC T521A / b FEATURES: DESCRIPTION: • Equivalent to AMD’s Am29520/21 bipolar Multilevel Pipeline Registers in pinout/function, speeds and output drive over full temperature and voltage supply extremes
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IDT29FCT520A/B
T521A
Am29520/21
IDT29FCT520A/B
IDT29FCT521A/B
IDT29FCT
MIL-STD-883,
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Untitled
Abstract: No abstract text available
Text: HIGH-PERFORMANCE CMOS BUFFERS ¡n í^ r r í^ o IDT54/74FCT828A/B FEATURES: DESCRIPTION: • Faster than AMD’s Am29827-28 series The IDT54/74FCT800 Series is built using advanced CEMOS , a dual metal CMOS technology. The IDT54/74FCT827A/B and IDT54/74FCT828A/B 10-bit bus
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IDT54/74FCT828A/B
Am29827-28
IDT54/74FCT800
IDT54/74FCT827A/B
IDT54/74FCT828A/B
10-bit
200mV
IDT54/74FCT827A/B-IDT54/74FCT828A/B
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Untitled
Abstract: No abstract text available
Text: lljljfiv Integrated DeviœTèchnology. Inc PRELIMINARY IDT 7320 IDT 7321 16-BIT CMOS MULTILEVEL PIPELINE REGISTERS FEATURES: DESCRIPTION • IDT7320: E ig h t 16-bit h ig h -sp e e d p ip e lin e registers • IDT7321: S even 16-bit h ig h -s p e e d p ip e lin e re giste rs p lu s a
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16-BIT
IDT7320:
IDT7321:
IDT7321
T7320
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Untitled
Abstract: No abstract text available
Text: MOTOROLA Military 54LS04 Hex-Input Inverter Gate ELECTRICALLY TESTED PER: MIL-M-38510/30003 M Vqc A6 Y6 A5 Y5 A4 P 0 lllllll LOGIC DIAGRAM Y4 AVAILABLE AS: 1 JAN: JM38510/30003BXA 2) SMD: N/A 3)883: 54LS04/BXAJC X = CASE OUTLINE AS FOLLOWS: PACKAGE: CERDIP: C
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54LS04
MIL-M-38510/30003
JM38510/30003BXA
54LS04/BXAJC
56A-02
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Untitled
Abstract: No abstract text available
Text: MOTOROLA M ilita ry 54L S 2 6 6 Quad 2-In pu t Exclusive NOR G ate ELECTRICALLY TESTED PER: MIL-M-38510/30303 MPO unw LOGIC DIAGRAM Vcc B4 A4 Y3 B3 A3 AVAILABLE AS: ? A1 Y4 1 JAN: JM38510/30303BXA 2) SMD: N/A 3)883: 54LS266/BXAJC <51 B1 Y1 Y2 A2 B2 X = CASE OUTLINE AS FOLLOWS:
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MIL-M-38510/30303
JM38510/30303BXA
54LS266/BXAJC
56A-02
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54ALS08
Abstract: Y411
Text: MOTOROLA Military 54ALS08 Quad 2-Input Positive AND Gate ELECTRICALLY TESTED PER: MPG54ALS08 AVAILABLE A S: L O G IC D IA G R A M B4 Vqc fi^l A4 Y4 B3 Rai Rii F I A3 1 JAN : N/A 2) SM D: N/A 3) 883C: 54ALS08/BXAJC Y3 nói ITI ITI X = C A S E OUTLINE A S FO LLOW S:
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MPG54ALS08
54ALS08
MiL-STD-843
Y411
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Untitled
Abstract: No abstract text available
Text: M MOTOROLA M ilita ry 5 4 F 1 3 2 Quad 2-In p u t NAND S c h m itt TVigger ELECTRICALLY TESTED PER: MPG54F132 H P O m B4 A4 Y4 B3 i AVAILABLE AS: LOGIC DIAGRAM VCC in A3 1) JAN: N/A 2) SMD: N/A 3)883: 54F132/BXAJC Y3 X = CASE OUTLINE AS FOLLOWS: PACKAGE: CERDIP: C
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MPG54F132
54F132/BXAJC
56A-02
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Untitled
Abstract: No abstract text available
Text: CO æ jg i National Æiâ Semiconductor DM54S86/DM74S86 Quad 2-Input Exclusive-OR Gates General Description This device contains four independent gates each of which performs the logic Exclusive-OR function. Connection Diagram Dual-In-Line Package V cc | 14
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DM54S86/DM74S86
DM54S86J,
DM54S86W
DM74S86N
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PDF
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Untitled
Abstract: No abstract text available
Text: g Military 54LS32 MOTOROLA Quad 2-Input OR Gate MP0 mini ELECTRICALLY TESTED PER: MIL-M-38510/30501 LOGIC DIAGRAM VCC ra B4 A4 [iii n il Y4 im B3 Hoi A3 in Y3 nn AVAILABLE AS: 1) JAN: JM38510/30501BXA 2) SMD: N/A 3)883: 54LS32/BXAJC X = CASE OUTLINE AS FOLLOWS:
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54LS32
MIL-M-38510/30501
JM38510/30501BXA
54LS32/BXAJC
56A-02
1N3064
1N3064
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Untitled
Abstract: No abstract text available
Text: MM54HCT139/MM74HCT139 National Semiconductor PRELIMINARY microCMOS M M 54H C T 139/M M 74H C T 13 9 D u al 2-TO -4 L in e D e c o d e r General Description The MM54HCT139/MM74HCT139 is a high speed sllicongate CMOS decoder that is well suited to memory address
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MM54HCT139/MM74HCT139
139/M
MM54HCT139/MM74HCT139
74HCT
54HCT
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SN54ALS138
Abstract: SN54AS138 SN74ALS138 SN74AS138
Text: SN 54A LS138, S N 54A S 138, SN 74A LS138, SN 74A S138 3-LINE TO 8 LINE DECODERS/DEMULTIPLEXERS D 2 6 6 1 , A P R IL 1 9 8 2 - R E V IS E D M A Y 1 9 8 6 S N 5 4 A L S 1 3 8 , S N 5 4 A S 1 3 8 . . . J PACKAGE S N 7 4 A L S 1 3 8 , S N 7 4 A S 1 3 8 . . . D OR N PACKAGE
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SN54ALS138,
SN54AS138,
SN74ALS138,
SN74AS138
D2661,
300-mil
SN54AS138
SN74AS138
SN54ALS138
SN54AS138
SN74ALS138
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74ABT125
Abstract: 74ABT125D 74ABT125N 74ABT125PW
Text: Philips Sem iconductors Product specification Quad buffer 3-State 74ABT125 FEATURES DESCRIPTION • Q uad bus interface The 74ABT125 high-perform ance BiCMOS device com bines low static and dynam ic power dissipation with high speed and high output drive.
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74ABT125
64mA/-32mA
500mA
REFEREN14:
SQT402-1
MO-153
74ABT125D
74ABT125N
74ABT125PW
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74ALS541A
Abstract: No abstract text available
Text: TYPES SN54ALS540, SN54ALS541, SN74ALS540, SN74ALS541 OCTAL BUFFERS AND LINE DRIVERS WITH 3 STATE OUTPUTS D2661. APRIL 1982-REVISED DECEMBER 1983 3-S tate Outputs Drive Bus Lines or Buffer Mem ory Address Registers S N 5 4 A L S 5 4 0 , S N 5 4 A L S 5 4 1 . . . J PACKAGE
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SN54ALS540,
SN54ALS541,
SN74ALS540,
SN74ALS541
D2661.
1982-REVISED
LS540
LS541
74ALS541A
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AHC540
Abstract: SN54AHC540 SN74AHC540
Text: SN54AHC540, SN74AHC540 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS260C - DECEMBER 1995 - REVISED JUNE 1996 Operating Range 2-V to 5.5-V Vqc SN54AHC 540 . . . J OR W PACKAGE SN74AHC 540 . . . DB, DW, N, OR PW PACKAGE TO P VIEW EPIC (Enhanced-Performance Implanted
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SN54AHC540,
SN74AHC540
SCLS260C
AHC540
SN54AHC540
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