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    V960PBC Price and Stock

    Rochester Electronics LLC V960PBC-33LP

    BUS CONTROLLER, PQFP160
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    DigiKey V960PBC-33LP Bulk 6
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    QuickLogic Corporation V960PBC-33LP

    V960PBC-33LP
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    Verical V960PBC-33LP 96 6
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    • 100 $61.925
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    Rochester Electronics V960PBC-33LP 458 1
    • 1 $50.55
    • 10 $50.55
    • 100 $47.52
    • 1000 $42.97
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    V960PBC Datasheets (8)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    V960PBC QuickLogic Interface: Local Bus to PCI Bridge Original PDF
    V960PBC-33 QuickLogic LOCAL BUS TO PCI BRIDGE CONTROLLERS Original PDF
    V960PBC-33LP QuickLogic Local Bus To Pci Bridge Original PDF
    V960PBC-33LPN REV B2 QuickLogic processor: LOCAL BUS TO PCI BRIDGE For i960 Sx PROCESSORS Original PDF
    V960PBC-33LPREVB2 QuickLogic processor: LOCAL BUS TO PCI BRIDGE For i960 Sx PROCESSORS Original PDF
    V960PBC-33 REV B2 QuickLogic LOCAL BUS TO PCI BRIDGE CONTROLLERS Original PDF
    V960PBC-33REVB2 QuickLogic Local bus to PCI bridge for i960SA/SB processors. Frequency 33 MHz. Original PDF
    V960PBC-33REVB2 QuickLogic LOCAL BUS TO PCI BRIDGE CONTROLLER Original PDF

    V960PBC Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    V292PBC

    Abstract: V960PBC V961PBC V962PBC
    Text: V3 Technical Note July 10, 1998 Stepping Change Notification: PBC ‘B2’ Step to EPC ‘A0’ Step Rev 1.30 Includes the V292PBC, V960PBC, V961PBC, and V962PBC EPC ‘A0’ was previously referred to as stepping PBC ‘C0’ The PBC is currently shipping at stepping level ‘B2’. In Q2 1997 V3 Semiconductor


    Original     		PDF V292PBC, V960PBC, V961PBC, V962PBC V961PBC V962PBC V292PBC V960PBC

    AD11

    Abstract: AD12 AD14 AD30 V960PBC V960PBC-33 V961PBC V96SSC 160-Pin Flat Package pci bridge sda 4211
    Text: V960PBC Rev. B2 LOCAL BUS TO PCI BRIDGE FOR i960Sx PROCESSORS • Dual bi-directional address space remapping • Glueless interface between Intel i960Sx, processors and PCI bus • On-the-fly byte order endian conversion • Fully compliant with PCI 2.1 specification


    Original     		PDF V960PBC i960Sx, LAD24" V961PBC. V960PBC AD11 AD12 AD14 AD30 V960PBC-33 V961PBC V96SSC 160-Pin Flat Package pci bridge sda 4211

    PPC401GF

    Abstract: V292PBC V960PBC V960PBC-33 V961PBC V961PBC-33 V961PBC-40 V962PBC V962PBC-33 V962PBC-40
    Text: VxxxPBC Rev. B2 LOCAL BUS TO PCI BRIDGE CONTROLLERS Data Sheet Addendum • I2OTM ready hardware messaging unit • Large, 576-byte FIFOs using V3’s unique DYNAMIC BANDWIDTH ALLOCATION architecture • 2 channel DMA controller • 33MHz and 40MHz local bus versions available


    Original     		PDF 576-byte 33MHz 40MHz 33MHz V960PBC V961PBC 2348G PPC401GF V292PBC V960PBC-33 V961PBC-33 V961PBC-40 V962PBC V962PBC-33 V962PBC-40

    AD29

    Abstract: AD30 V350EPC V350EPC-33 V350EPC-40 V960PBC V961PBC V96BMC
    Text: V350EPC Rev. A0 LOCAL BUS TO PCI BRIDGE FOR MULTIPLEXED A/D PROCESSORS • Glueless interface to Intel’s i960Jx and IBM’s PowerPCTM 401Gx processors • On-the-fly byte order endian conversion • I2O ATU and messaging unit including hardware controlled circular queues


    Original     		PDF V350EPC i960Jx 401Gx 640-byte 64-byte V350EPC 2348G AD29 AD30 V350EPC-33 V350EPC-40 V960PBC V961PBC V96BMC

    AD29

    Abstract: AD30 V350EPC V350EPC-33 V350EPC-40 V960PBC V961PBC V96BMC
    Text: V350EPC Rev. A0 / A1 LOCAL BUS TO PCI BRIDGE FOR MULTIPLEXED A/D PROCESSORS • Glueless interface to Intel’s i960Jx and IBM’s PowerPC TM 401Gx processors • On-the-fly byte order endian conversion • I2O ATU and messaging unit including hardware controlled circular queues


    Original     		PDF V350EPC i960Jx 401Gx 640-byte 64-byte V350EPC 2348G AD29 AD30 V350EPC-33 V350EPC-40 V960PBC V961PBC V96BMC

    AD12

    Abstract: AD14 AD30 V292PBC V962PBC V962PBC-33 V962PBC-40 V96BMC
    Text: V962PBC Rev. B2 LOCAL BUS TO PCI BRIDGE FOR DE-MULTIPLEXED A/D PROCESSORS • Dual bi-directional address space remapping • Glueless interface between Intel i960 Cx/Hx processors and PCI bus • On-the-fly byte order endian conversion • Fully compliant with PCI 2.1 specification


    Original     		PDF V962PBC 16MHz 40MHz V962PBC AD12 AD14 AD30 V292PBC V962PBC-33 V962PBC-40 V96BMC

    Untitled

    Abstract: No abstract text available
    Text: V961PBC Rev. B2 LOCAL BUS TO PCI BRIDGE FOR MUTLTELEXED A/D PROCESSORS • Dual bi-directional address space remapping • Glueless interface between Intel i960Jx, IBM PPC401Gx, processors and PCI bus • On-the-fly byte order endian conversion • Fully compliant with PCI 2.1 specification


    Original     		PDF V961PBC i960Jx, PPC401Gx, 8/16-bit i960Jx PPC401Gx 16MHz 40MHz

    I960SX

    Abstract: No abstract text available
    Text: V350EPC Rev. A0 LOCAL BUS TO PCI BRIDGE FOR MULTIPLEXED A/D PROCESSORS • Glueless interface to Intel’s i960Jx and IBM’s PowerPCTM 401Gx processors • On-the-fly byte order endian conversion • I2O ATU and messaging unit including hardware controlled circular queues


    Original     		PDF V350EPC i960Jx 401Gx 640-byte 64-byte 8/16-bit 32-bit 16-bit I960SX

    heartbeat counter

    Abstract: PPC401GF V960PBC V961PBC V96SSC V96SSC-33LP AD1065 ppc401
    Text: V96SSC Rev. B1 HIGH-INTEGRATION SYSTEM CONTROLLER FOR i960Sx/Jx AND PowerPC 401Gx PROCESSORS • Direct interface to i960Sx/Jx and PPC401Gx processors • High-performance burst DRAM controller • System watchdog and heartbeat timers • 16 general purpose I/O bits


    Original     		PDF V96SSC 401Gx i960Sx/Jx PPC401Gx 33MHz 8/16-bit 100-pin i960Sx i960Jx 32-bit heartbeat counter PPC401GF V960PBC V961PBC V96SSC-33LP AD1065 ppc401

    AD14

    Abstract: AD30 PPC401GF V292PBC V961PBC V961PBC-33 V961PBC-40 V96BMC V96SSC
    Text: V961PBC Rev. B2 LOCAL BUS TO PCI BRIDGE FOR MULTIPLEXED A/D PROCESSORS • Glueless interface between Intel i960Jx, IBM PPC401Gx, processors and PCI bus • Dual bi-directional address space remapping • On-the-fly byte order endian conversion • Fully compliant with PCI 2.1 specification


    Original     		PDF V961PBC i960Jx, PPC401Gx, 16MHz 40MHz AD14 AD30 PPC401GF V292PBC V961PBC-33 V961PBC-40 V96BMC V96SSC

    Untitled

    Abstract: No abstract text available
    Text: V960PBC Rev. B2 LOCAL BUS TO PCI BRIDGE FOR ¡960 Sx PROCESSORS • Glueless interface between Intel ¡960Sx, processors and PCI bus • Fully compliant with PCI 2.1 specification • Configurable for primary master, bus master, or target operation • Up to 1 Kbyte burst access support on both local


    OCR Scan     		PDF V960PBC 960Sx, 8/16-bit V960PBC LAD24â V961PBC.

    Untitled

    Abstract: No abstract text available
    Text: •iOONSna 0 0 0 0 0 4 7 V960PBC V 313 Rev. B1 LOCAL BUS TO PCI BRIDGE FOR i960 Sx PROCESSORS “ • Glueless interface between ¡960Sx processors and the PCI bus • Large, 576-byte FIFOs using V3’s unique D y n a m ic B a n d w id t h A l l o c a t i o n architecture


    OCR Scan     		PDF V960PBC 960Sx 576-byte 33MHz 160-pin V960PBC, V961PBC, V962PBC, V292PBC

    V96SSC25LP

    Abstract: No abstract text available
    Text: ‘ÌOOMEOO 0 0 0 0 3 0 3 ISA V96SSC • * * ▼ / Rev. BO HIGH-INTEGRATION SYSTEM CONTROLLER FOR ¡960 Sx/Jx AND PowerPC 401 Gx PROCESSORS • Direct interface to ¡960Sx/Jx and PPC401Gx processors • High-performance burst DRAM controller • Two-channel fly-by DMA controller


    OCR Scan     		PDF V96SSC 25MHz 100-pin i960Sx i960Jx i960Sx/Jx PPC401Gx 8/16-bit 32-bit V96SSC V96SSC25LP

    Untitled

    Abstract: No abstract text available
    Text: V292PBC S LOCAL BUS TO PCI BRIDGE FOR DE-MULTIPLEXED A/D PROCESSORS • Glueless interface between AMD’s Am29030/ 40 processors and PCI bus • Fully compliant with PCI 2.1 specification • Configurable for primary master, bus master, or target operation


    OCR Scan     		PDF V292PBC Am29030/ 234SG

    Untitled

    Abstract: No abstract text available
    Text: T 0 Q 4 E D 0 D D D O H b b 212 V292BMC Rev. D HIGH PERFORMANCE BURST DRAM CONTROLLER :.V “ FOR Am29030/40 PROCESSORS • Pin/Software compatible with earlier V292BMC. • Integrated Page Cache Management. • Direct interfaces to Am29030/40 processors.


    OCR Scan     		PDF V292BMC Am29030/40 V292BMC. 512Mb 24-bit 40MHz 132-pin 160-pin V960PBC,

    V360EPC

    Abstract: 1gg7 Extended Sector Remapper V3 Semiconductor V350EPC design of dma controller using vhdl eeprom programmer schematic 24c02 V292PBC V960PBC V961PBC
    Text: Chapter 1 Introduction In a very short period of tim e the PCI bus standard has moved beyond the PC to become the most w idely accepted high-performance bus standard for embedded applications. As a leader in providing chipset solutions for high-end embedded applications, V3 Sem iconductor


    OCR Scan     		PDF Am29Kâ 960/Am29K V350EPC V96SSC V360EPC 1gg7 Extended Sector Remapper V3 Semiconductor design of dma controller using vhdl eeprom programmer schematic 24c02 V292PBC V960PBC V961PBC

    Untitled

    Abstract: No abstract text available
    Text: • V yf V962PBC f ^ « K O • Rev. B1 LOCAL BUS TO PCI BRIDGE FOR i960 Cx/Hx PROCESSORS / * 5 • Glueless interface between ¡960Cx/Hx processors and the PCI bus • 2 channel DMA controller • Bi-directional mailboxes w/doorbell interrupts • Large, 576-byte FIFOs using V 3 ’s unique


    OCR Scan     		PDF V962PBC 960Cx/Hx 576-byte 33MHz 16MHz 40MHz

    Untitled

    Abstract: No abstract text available
    Text: • TD042DD 0000132 V292PBC 117 Rev. B1 LOCAL BUS TO PCI BRIDGE FOR Am29K PROCESSORS '« IC O * ” ’ • Glueless interface between Am29030/40 processors and the PCI bus • Large, 576-byte FIFOs using V3’s unique D y n a m ic B a n d w id t h A l l o c a t i o n ™ architecture


    OCR Scan     		PDF TD042DD V292PBC Am29Kâ Am29030/40 576-byte 33MHz i00420D 160-pin V960PBC, V961PBC,

    PJ3N

    Abstract: No abstract text available
    Text: . . y lf • * ▼ • =1004200 0 0 0 0 0 2 1 V96DPC f « 450 ■ Rev. B1 LOCAL BUS TO PCI BRIDGE FOR i960 Cx/Hx/Jx/Sx AND PowerPC 40lGx PROCESSORS • Glueless interface between i960Sx/Jx/Cx/Hx, PPC401 Gx processors and two PCI buses • On-the-fly byte order endian conversion


    OCR Scan     		PDF V96DPC 40lGx i960Sx/Jx/Cx/Hx, PPC401 160-pin VU1150A V960PBC, V961PBC, V962PBC, V292PBC PJ3N

    Untitled

    Abstract: No abstract text available
    Text: Chapter 1 Introduction In a very short period of tim e the PCI bus standard has moved beyond the PC to become the most w idely accepted high-perform ance bus standard for embedded applications. As a leader in providing chipset solutions for high-end embedded applications, V3 Sem iconductor


    OCR Scan     		PDF Am29Kâ 960/Am29K V350EPC pin91 V96SSC

    Untitled

    Abstract: No abstract text available
    Text: V962PBC S LOCAL BUS TO PCI BRIDGE FOR DE-MULTIPLEXED A/D PROCESSORS • Glueless interface between Intel ¡960 Cx/Hx processors and PCI bus • Fully compliant with PCI 2.1 specification • Configurable for primary master, bus master, or target operation


    OCR Scan     		PDF V962PBC 234SG

    Untitled

    Abstract: No abstract text available
    Text: - V 9 6 1 P B C Rev. B1 LOCAL BUS TO PCI BRIDGE FOR i960 Jx AND PowerPC 401 Gx PROCESSORS yi '« IC O * ’ • Glueless interface between i960Jx, PPC401Gx processors and the PCI bus • Large, 576-byte FIFOs using V3’s unique D y n a m ic B a n d w id t h A l l o c a t io n ™ architecture


    OCR Scan     		PDF i960Jx, PPC401Gx 576-byte 33MHz 16MHz 40MHz

    Untitled

    Abstract: No abstract text available
    Text: V961PBC Rev. B2 LOCAL BUS TO PCI BRIDGE FOR MUTLTELEXED A/D PROCESSORS • Glueless interface between Intel ¡960Jx, IBM PPC401Gx, processors and PCI bus • Fully compliant with PCI 2.1 specification • Configurable for primary master, bus master, or target operation


    OCR Scan     		PDF V961PBC 960Jx, PPC401Gx, 8/16-bit V961PBC 234SG

    Untitled

    Abstract: No abstract text available
    Text: • S00M200 V96BMC jj ; v D000M54 STO Rev. D HIGH PERFORMANCE BURST DRAM CONTROLLER - FOR i960Cx/Hx/Jx PROCESSORS • Pin/Software compatible with earlier V96BMC. • Integrated Page Cache Management. • Direct interfaces to i960Cx/Hx/Jx processors. • 2Kbyte burst transaction support.


    OCR Scan     		PDF S00M200 V96BMC D000M54 i960Cx/Hx/Jx V96BMC. i960Cx/Hx/Jx 512Mb 24-bit 40MHz 132-pin