V96DPC Search Results

PJ3N

Contextual Info: . . y lf • * ▼ • =1004200 0 0 0 0 0 2 1 V96DPC f « 450 ■ Rev. B1 LOCAL BUS TO PCI BRIDGE FOR i960 Cx/Hx/Jx/Sx AND PowerPC 40lGx PROCESSORS • Glueless interface between i960Sx/Jx/Cx/Hx, PPC401 Gx processors and two PCI buses • On-the-fly byte order endian conversion

V96SSC25LP

Contextual Info: ‘ÌOOMEOO 0 0 0 0 3 0 3 ISA V96SSC • * * ▼ / Rev. BO HIGH-INTEGRATION SYSTEM CONTROLLER FOR ¡960 Sx/Jx AND PowerPC 401 Gx PROCESSORS • Direct interface to ¡960Sx/Jx and PPC401Gx processors • High-performance burst DRAM controller • Two-channel fly-by DMA controller

Contextual Info: ^004200 □□□□102 MST • V961PBC •" V Rev. B1 LOCAL BUS TO PCI BRIDGE FOR i960 Jx AND PowerPC 401 Gx PROCESSORS " • Glueless interface between ¡960Jx, PPC401 Gx processors and the PCI bus • Large, 576-byte FIFOs using V3's unique D y n a m ic B a n d w id t h A l l o c a t i o n ™ architecture

Contextual Info: T 0 Q 4 E D 0 D D D O H b b 212 V292BMC Rev. D HIGH PERFORMANCE BURST DRAM CONTROLLER :.V “ FOR Am29030/40 PROCESSORS • Pin/Software compatible with earlier V292BMC. • Integrated Page Cache Management. • Direct interfaces to Am29030/40 processors.

Contextual Info: • TD042DD 0000132 V292PBC 117 Rev. B1 LOCAL BUS TO PCI BRIDGE FOR Am29K PROCESSORS '« IC O * ” ’ • Glueless interface between Am29030/40 processors and the PCI bus • Large, 576-byte FIFOs using V3’s unique D y n a m ic B a n d w id t h A l l o c a t i o n ™ architecture

Contextual Info: •iOONSna 0 0 0 0 0 4 7 V960PBC V 313 Rev. B1 LOCAL BUS TO PCI BRIDGE FOR i960 Sx PROCESSORS “ • Glueless interface between ¡960Sx processors and the PCI bus • Large, 576-byte FIFOs using V3’s unique D y n a m ic B a n d w id t h A l l o c a t i o n architecture

Contextual Info: • S00M200 V96BMC jj ; v D000M54 STO Rev. D HIGH PERFORMANCE BURST DRAM CONTROLLER - FOR i960Cx/Hx/Jx PROCESSORS • Pin/Software compatible with earlier V96BMC. • Integrated Page Cache Management. • Direct interfaces to i960Cx/Hx/Jx processors. • 2Kbyte burst transaction support.

Contextual Info: TG04200 if QQQD117 V 9 6 2 P B C SÔQ Rev. B1 LOCAL BUS TO PCI BRIDGE FOR i960 Cx/Hx PROCESSORS » Ic0* v • Glueless interface between i960Cx/Hx processors and the PCI bus • 2 channel DMA controller • Bi-directional mailboxes w/doorbell interrupts • Large, 576-byte FIFOs using V3’s unique