V96DPC Search Results

V96DPC Datasheets Context Search

Catalog Datasheet	MFG & Type	PDF	Document Tags
PJ3N Abstract: No abstract text available Text: . . y lf • * ▼ • =1004200 0 0 0 0 0 2 1 V96DPC f « 450 ■ Rev. B1 LOCAL BUS TO PCI BRIDGE FOR i960 Cx/Hx/Jx/Sx AND PowerPC 40lGx PROCESSORS • Glueless interface between i960Sx/Jx/Cx/Hx, PPC401 Gx processors and two PCI buses • On-the-fly byte order endian conversion	OCR Scan	PDF	V96DPC 40lGx i960Sx/Jx/Cx/Hx, PPC401 160-pin VU1150A V960PBC, V961PBC, V962PBC, V292PBC PJ3N
V96SSC25LP Abstract: No abstract text available Text: ‘ÌOOMEOO 0 0 0 0 3 0 3 ISA V96SSC • * * ▼ / Rev. BO HIGH-INTEGRATION SYSTEM CONTROLLER FOR ¡960 Sx/Jx AND PowerPC 401 Gx PROCESSORS • Direct interface to ¡960Sx/Jx and PPC401Gx processors • High-performance burst DRAM controller • Two-channel fly-by DMA controller	OCR Scan	PDF	V96SSC 25MHz 100-pin i960Sx i960Jx i960Sx/Jx PPC401Gx 8/16-bit 32-bit V96SSC V96SSC25LP
Untitled Abstract: No abstract text available Text: ^004200 □□□□102 MST • V961PBC •" V Rev. B1 LOCAL BUS TO PCI BRIDGE FOR i960 Jx AND PowerPC 401 Gx PROCESSORS " • Glueless interface between ¡960Jx, PPC401 Gx processors and the PCI bus • Large, 576-byte FIFOs using V3's unique D y n a m ic B a n d w id t h A l l o c a t i o n ™ architecture	OCR Scan	PDF	V961PBC 960Jx, PPC401 576-byte 33MHz 160-pin V960PBC, V961PBC, V962PBC, V292PBC
Untitled Abstract: No abstract text available Text: T 0 Q 4 E D 0 D D D O H b b 212 V292BMC Rev. D HIGH PERFORMANCE BURST DRAM CONTROLLER :.V “ FOR Am29030/40 PROCESSORS • Pin/Software compatible with earlier V292BMC. • Integrated Page Cache Management. • Direct interfaces to Am29030/40 processors.	OCR Scan	PDF	V292BMC Am29030/40 V292BMC. 512Mb 24-bit 40MHz 132-pin 160-pin V960PBC,
Untitled Abstract: No abstract text available Text: • TD042DD 0000132 V292PBC 117 Rev. B1 LOCAL BUS TO PCI BRIDGE FOR Am29K PROCESSORS '« IC O * ” ’ • Glueless interface between Am29030/40 processors and the PCI bus • Large, 576-byte FIFOs using V3’s unique D y n a m ic B a n d w id t h A l l o c a t i o n ™ architecture	OCR Scan	PDF	TD042DD V292PBC Am29Kâ Am29030/40 576-byte 33MHz i00420D 160-pin V960PBC, V961PBC,
Untitled Abstract: No abstract text available Text: •iOONSna 0 0 0 0 0 4 7 V960PBC V 313 Rev. B1 LOCAL BUS TO PCI BRIDGE FOR i960 Sx PROCESSORS “ • Glueless interface between ¡960Sx processors and the PCI bus • Large, 576-byte FIFOs using V3’s unique D y n a m ic B a n d w id t h A l l o c a t i o n architecture	OCR Scan	PDF	V960PBC 960Sx 576-byte 33MHz 160-pin V960PBC, V961PBC, V962PBC, V292PBC
Untitled Abstract: No abstract text available Text: • S00M200 V96BMC jj ; v D000M54 STO Rev. D HIGH PERFORMANCE BURST DRAM CONTROLLER - FOR i960Cx/Hx/Jx PROCESSORS • Pin/Software compatible with earlier V96BMC. • Integrated Page Cache Management. • Direct interfaces to i960Cx/Hx/Jx processors. • 2Kbyte burst transaction support.	OCR Scan	PDF	S00M200 V96BMC D000M54 i960Cx/Hx/JxÂ V96BMC. i960Cx/Hx/Jx 512Mb 24-bit 40MHz 132-pin
Untitled Abstract: No abstract text available Text: TG04200 if QQQD117 V 9 6 2 P B C SÔQ Rev. B1 LOCAL BUS TO PCI BRIDGE FOR i960 Cx/Hx PROCESSORS » Ic0* v • Glueless interface between i960Cx/Hx processors and the PCI bus • 2 channel DMA controller • Bi-directional mailboxes w/doorbell interrupts • Large, 576-byte FIFOs using V3’s unique	OCR Scan	PDF	TG04200 QQQD117 i960Cx/Hx 576-byte 33MHz 160-pin V960PBC, V961PBC, V962PBC, V292PBC