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    ULTRA3800 Search Results

    ULTRA3800 Datasheets (4)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    Ultra38003 Cypress Semiconductor UltraLogic Very High Speed 3K Gate CMOS FPGA Scan PDF
    Ultra38005 Cypress Semiconductor UltraLogic Very High Speed 5K Gate CMOS FPGA Scan PDF
    Ultra38007 Cypress Semiconductor UltraLogic Very High Speed 7K Gate CMOS FPGA Scan PDF
    Ultra38009 Cypress Semiconductor UltraLogic Very High Speed 9K Gate CMOS FPGA Scan PDF

    ULTRA3800 Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    n20s

    Abstract: A144 BG256 IEEE1164 Military Plastic pASIC 3 Family 256
    Text: 3T PRELIMINARY CYPRESS Ultra38007 UltraLogic Very High Speed 7K Gate CMOS FPGA Features — Minimum Iol and Ioh 24 mA Flexible logic cell architecture — Wide fan-in up to 16 input gates — Multiple outputs in each cell — Very low cell propagation delay


    OCR Scan     		144-pin 208-pin 256-pin 16-bit Ultra38007 208-Pin CY38007P20 CY38007P144â n20s A144 BG256 IEEE1164 Military Plastic pASIC 3 Family 256 PDF

    CY38007P144-1AC

    Abstract: CY38007P144-1AI CY38007P144-2AC CY38007P144-2AI CY38007P208-2NC CY38007P208-2NI CY38007P256-1BGC CY38007P256-2BGC IEEE1164
    Text: 7c3807: Tuesday, July 25, 1995 Rev date: October 25, 1995 PRELIMINARY UltraLogic Ultra38007 t Very High Speed 7K Gate CMOS FPGA Features Ċ D Very high speed Loadable counter frequencies greater than 185 MHz Ċ ChipĆtoĆchip operating frequencies up to 135 MHz


    Original     		7c3807: Ultra38007 144pin 208pin 256pin 16bit CY38007P144-1AC CY38007P144-1AI CY38007P144-2AC CY38007P144-2AI CY38007P208-2NC CY38007P208-2NI CY38007P256-1BGC CY38007P256-2BGC IEEE1164 PDF

    7C380

    Abstract: No abstract text available
    Text: 7c3803: October 12, 1995 Revised: October 24, 1995 Ultra38003 ADVANCED INFORMATION UltraLogict Very High Speed 3K Gate CMOS FPGA D Robust routing resources Features D Very high speed D D D D D D Ċ Loadable counter frequencies greater than 185 MHz Ċ ChipĆtoĆchip operating frequencies


    Original     		7c3803: Ultra38003 84pin 144pin Ultra38000t Ultra38000 7C380031 Ultra3800, 7C380 PDF

    Untitled

    Abstract: No abstract text available
    Text: W / CYPRESS ADVANCED INFORMATION Ultra38003 UltraLogic Very High Speed 3K Gate CMOS FPGA Features • Very high speed — Loadable counter frequencies greater than 185 MHz — Chip-to-chip operating frequencies up to 135 MHz — Input + logic cell + output delays


    OCR Scan     		Ultra38003 84-pin 144-pin 16-bit Ultra38000â Ultra38000 Ultra38000, PDF

    Untitled

    Abstract: No abstract text available
    Text: 7c3809: October 9, 1995 Revision: October 25, 1995 Ultra38009 ADVANCED INFORMATION UltraLogict Very High Speed 9K Gate CMOS FPGA D Robust routing resources Features D Very high speed D D D D D D Ċ Loadable counter frequencies greater than 185 MHz Ċ ChipĆtoĆchip operating frequencies


    Original     		7c3809: Ultra38009 144pin 208pin 256pin Ultra3800t Ultra3800 7C380091 Ultra3800, PDF

    IEEE1164

    Abstract: 5-input-XOR schematic of TTL XOR Gates cy7c38003 3-input-XOR
    Text: Ultra3800: October 13, 1995 Revision: October 25, 1995 PRELIMINARY Ċ Loadable counter frequencies greater than 185 MHz Ċ Data Path frequencies at greater than 200 MHz Ċ ChipĆtoĆchip operating frequencies up to 135 MHz Ċ Input + logic cell + output delays


    Original     		Ultra3800: IEEE1164 5-input-XOR schematic of TTL XOR Gates cy7c38003 3-input-XOR PDF

    Untitled

    Abstract: No abstract text available
    Text: PRESS RELEASE CYPRESS BROADENS Warp SOFTWARE SUPPORT Offers Support for LPM and Ultra38000 FPGAs, Introduces Low-Cost Simulation Product SAN JOSE, Calif., December 16, 1996 - In a move geared to extend its leadership in low-cost, high-quality programmable logic design tools, Cypress Semiconductor Corp.


    Original     		Ultra38000 FLASH370i, PDF

    Untitled

    Abstract: No abstract text available
    Text: 7c3805: October 5, 1995 Revision: October 25, 1995 ADVANCED INFORMATION Ultra38005 UltraLogict Very High Speed 5K Gate CMOS FPGA D Robust routing resources Features D Very high speed D D D D D D Ċ Loadable counter frequencies greater than 185 MHz Ċ ChipĆtoĆchip operating frequencies


    Original     		7c3805: Ultra38005 84pin 144pin 208pin Ultra38000t Ultra38000 7C380051 Ultra3800, PDF

    loadable counter

    Abstract: No abstract text available
    Text: ADVANCED INFORMATION m .7 Ultra38016 C Y P R E S S UltraLogic Very High Speed 16K Gate CMOS FPGA Features • Very high speed — Loadable counter frequencies greater than 185 MHz — Chip-to-chip operating frequencies up to 135 MHz — Input + logic cell + output delays


    OCR Scan     		Ultra38016 208-pin 352-pin 16-bit 00EBEEBE0BB0 BE0000000000 00BBBEBE0EBB 00BEBEE00000I E00000BEB00EI EB0000EEE00EI loadable counter PDF

    Untitled

    Abstract: No abstract text available
    Text: CYPRESS Features • Very high speed — Loadable counter frequencies greater than 185 MHz — Chip-to-chip operating frequencies up to 135 MHz — Input + logic cell + output delays under 5.5 ns • Unparalleled FPGA performance for counters, data path, state machines,


    OCR Scan     		Ultra38012 208-pin 352-pin 16-bit Ii15111gt11g111511ifi 0EEEEBBEEBEB00B0 Ultra38000, PDF

    loadable counter

    Abstract: No abstract text available
    Text: CYPRESS Features • Full 3.3V operation • Very high speed — Loadable counter frequencies greater than 100 MHz — Chip-to-chip operating frequencies up to 85 MHz — Input + logic cell + output delays under 7 ns • Unparalleled FPGA performance for counters, data path, state machines,


    OCR Scan     		208-pin 352-pin 16-bit 7C338012-1 Ultra38000, loadable counter PDF

    Untitled

    Abstract: No abstract text available
    Text: = / CYPRESS ADVANCED INFORMATION Ultra338005 UltraLogic Very High Speed 5K Gate 3.3V CMOS FPGA Features • Fall 3.3V operation • Very high speed — Loadable counter frequencies greater than 100 MHz — Chip-to-chip operating frequencies up to 85 MHz


    OCR Scan     		of320 84-pin 144-pin 208-pin 16-bit Ultra38000â Ultra38000 0000BE Ultra38000, PDF

    AAAG 6 pin ic

    Abstract: n208
    Text: CYPRESS Features PRELIMINARY UltraLogic Very High Speed 7K Gate CMOS FPGA — Minimum Iol and Ioh ° f 24 mA • Flexible logic cell architecture — Wide fan-in up to 16 input gates — Multiple outputs in each cell — Very low cell propagation delay


    OCR Scan     		144-Pin 256-Pad 208-Pin AAAG 6 pin ic n208 PDF

    Untitled

    Abstract: No abstract text available
    Text: CYPRESS Features • Very high speed — Loadable counter frequencies greater than 185 MHz — Chip-to-chip operating frequencies up to 135 MHz — Input + logic cell + output delays under 5.5 ns • Unparalleled FPGA performance for counters, data path, state machines,


    OCR Scan     		Ultra38016 0EE00ERRRRRE 0EE00EEBHEEE 0E0EQE0000E0 0EE00EE000EE 0EEH0EHH00EE 0E0E0E0000E0 0E000EE0HEEE 0EEE0EE00EEE 000E0E0000EE PDF

    Untitled

    Abstract: No abstract text available
    Text: F# CYPRESS Features • Full 3 J V operation • Very high speed — Loadable counter frequencies greater than 100 MHz — Chip-to-chip operating frequencies up to 85 MHz — Input + logic cell + output delays under 7 ns • Unparalleled FPGA performance for


    OCR Scan     		Ultra338003 16-bit 0000000FAi1000000 ltra38000, PDF

    Untitled

    Abstract: No abstract text available
    Text: f? CYPRESS Features • Very high speed — Loadable counter frequencies greater than 185 MHz — Chip-to-chip operating frequencies up to 135 MHz — Input + logic cell + output delays under 5.5 ns • U nparalleled FPGA performance for counters, data path, state machines,


    OCR Scan     		208-pin 352-pin 16-bit ga0000000000 E0E00000000B0000 0E000000000E0000 EE0E00EE0EEG3E000 EE00000000EE0000 ltra38000, PDF

    Untitled

    Abstract: No abstract text available
    Text: CYPRESS • Features • Very high speed — Loadable counter frequencies greater than 185 MHz — Chip-to-chip operating frequencies up to 135 MHz — Input + logic cell + output delays under 5.5 ns • U nparalleled FPGA performance for counters, data path, state machines,


    OCR Scan     		144-pin 208-pin 256-pin 16-bit B0B00E000BB0B00BBaBK E0B00B000BE000BBBS 0000E 000HE00000I EB00B0B00B0B0I BBEEEBBE0B0001 PDF

    architecture of cypress FLASH370 device

    Abstract: FLASH370
    Text: PRESS RELEASE CYPRESS ADDS NEW SYNTHESIS CAPABILITY, FPGA SUPPORT TO $99 WARP2 Leading VHDL Programming Tool Now Supports All Cypress PLDs, CPLDs, and FPGAs SAN JOSE, Calif., April 22, 1996 - Cypress Semiconductor Corp. today introduced Release 4 of its highly popular, $99 VHDL-based Warp2


    Original     		pASIC380 MAX340 FLASH370 1-800-WARP-VHDL FLASH370, architecture of cypress FLASH370 device PDF

    CISC AND RISC

    Abstract: 7C380
    Text: 7c3820: October 11, 1995 Revision: October 25, 1995 ADVANCED INFORMATION Ultra38020 UltraLogict Very High Speed 20K Gate CMOS FPGA Features D Very high speed D D D D D D Ċ Loadable counter frequencies greater than 185 MHz Ċ ChipĆtoĆchip operating frequencies


    Original     		7c3820: Ultra38020 208pin 352pin 16bit Ultra38000t Ultra38000 7C380201 Ultra3800, CISC AND RISC 7C380 PDF

    Untitled

    Abstract: No abstract text available
    Text: ADVANCED INFORMATION 5f CYPRESS UltraLogic Very High Speed 20K Gate 3.3V CMOS FPGA — Very low cell propagation delay 1.4 ns typical Features • Full 3.3V operation • Very high speed — Loadable counter frequencies greater than 100 MHz — Chip-8-chip operating frequencies


    OCR Scan     		208-pin 352-pin 16-bit 00BBBBBBBBEEEÂ 3000000BBBBB000000 0BBBBBBB0BB000BBBBBBBBFÂ 3H00B0000BBBEEH00B 1B0B000000BBHHHH0E1 000000EE00BBBB0B00 BE00BE0BBB00B000BE PDF

    Untitled

    Abstract: No abstract text available
    Text: CYPRESS Features • Very high speed — Loadable counter frequencies greater than 1SS MHz — Chip-to-chip operating frequencies up to 135 MHz — Input + logic cell + output delays under 5.5 ns • Unparalleled FPGA performance for counters, data path, state machines,


    OCR Scan     		Ultra38009 144-pin 208-pin 256-pin 16-bit I0000000000B 0000000000000000E1SIS00000000 E00E000E 00000000S00000000FwmmmmH0mm HE10000E1000B0I PDF

    84-PIN

    Abstract: Ultra38005
    Text: CYPRESS Features • Very high speed — Loadable counter frequencies greater than 185 MHz — Chip-to-chip operating frequencies up to 135 MHz — Input + logic cell + output delays under 5.5 ns • Unparalleled FPGA performance for counters, data path, state machines,


    OCR Scan     		Ultra38005 of320 84-pin 144-pin 208-pin 16-bit Ultra38000 Ultra38000 EEEE00000 0000QE3000 Ultra38005 PDF

    architecture of cypress FLASH370 device

    Abstract: architecture of cypress FLASH370 cpld FLASH370
    Text: PRESS RELEASE CYPRESS CPLDs ADD IN-SYSTEM REPROGRAMMABILITY FLASH370i Devices Also Offer PCI Compliance, Bus-Hold Feature SAN JOSE, Calif., July 15, 1996 - Taking advantage of the outstanding routability and fixed timing model of its FLASH370 family of complex programmable logic devices


    Original     		FLASH370iTM FLASH370TM FLASH370i FLASH370i, FLASH370, Ultra38000, architecture of cypress FLASH370 device architecture of cypress FLASH370 cpld FLASH370 PDF

    Untitled

    Abstract: No abstract text available
    Text: PRESS RELEASE CYPRESS, QUICKLOGIC ANNOUNCE INTENT TO AMEND FPGA AGREEMENT All Cypress Resources To Be Redirected to High-Density ISR Product Development SAN JOSE, California.February 10, 1997  Cypress Semiconductor Corp. [CY:NYSE] and QuickLogic Corp. today announced their intent to terminate an existing


    Original     		t1995: Flash370i PDF