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    TTL BUFFER Search Results

    TTL BUFFER Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    MM54C901J/883 Rochester Electronics LLC 54C901 - Hex Inverting TTL Buffer Visit Rochester Electronics LLC Buy
    9009DM/C Rochester Electronics LLC NAND Buffer 4-Input Gate, TTL, CDIP14 Visit Rochester Electronics LLC Buy
    74VHCT541AFT Toshiba Electronic Devices & Storage Corporation CMOS Logic IC, Octal Buffer, TSSOP20B Visit Toshiba Electronic Devices & Storage Corporation
    74VHC541FT Toshiba Electronic Devices & Storage Corporation CMOS Logic IC, Octal Buffer, TSSOP20B Visit Toshiba Electronic Devices & Storage Corporation
    7UL1G125NX Toshiba Electronic Devices & Storage Corporation One-Gate Logic(L-MOS), Buffer, XSON6, -40 to 125 degC Visit Toshiba Electronic Devices & Storage Corporation

    TTL BUFFER Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    740L6000

    Abstract: transistor c2026 c2026 c2026 transistor data 740L6010 transistor equivalent c2026 740L6011 C2026 TRANSISTOR 740L6001 c2037
    Text: HIGH-SPEED LOGIC-TO’LOGIC OPTOCOUPLERS OPTOELECTRONICS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER LSTTLto ORDER INFORMATION LOGIC COMPATIBILITY PART NUMBER INPUT OUTPUT TTL 740L6000 LSTTL TTL 740L6001 LSTTL CMOS 740L6010 LSTTL CMOS 740L6011 LSTTL


    OCR Scan     		740L6000 740L6001 740L6010 740L6011 740L6011 transistor c2026 c2026 c2026 transistor data transistor equivalent c2026 C2026 TRANSISTOR c2037 PDF

    MSI Logic

    Abstract: UT54ACS14E ut54acts541e UT54ACTS02E UT54ACS14 Tri-State Buffer CMOS cmos msi data book cmos TTL LOGIC DATA BOOK UT54ACS373
    Text: Aeroflex MSI Logic IBIS model Buffer Identification 4/16/2009 Tri-State Devices Input Buffer CMOS TTL Output Buffer 8mA 8mA UT54ACS273 UT54ACTS04 CMOS CMOS E TTL TTL (E) 8mA 8mA 8mA 8mA UT54ACS273 UT54ACS02E UT54ACTS04 UT54ACTS08E CMOS TTL 8mA 8mA UT54ACS273


    Original     		UT54ACS273 UT54ACTS04 UT54ACS02E UT54ACTS08E MSI Logic UT54ACS14E ut54acts541e UT54ACTS02E UT54ACS14 Tri-State Buffer CMOS cmos msi data book cmos TTL LOGIC DATA BOOK UT54ACS373 PDF

    PDU-1316F-1

    Abstract: PDU-1316F-10 PDU-1316F-12 PDU-1316F-2 PDU-1316F-3 PDU-1316F-4 PDU-1316F-5 PDU-1316F-6 PDU-1316F-8 1316F
    Text: Digitally Programmable Delav1 Units series : PDU-1316F 4-Bit TTL Interfaced Specifications: Features: • Input & output TTL buffered ■ 4-BIT TTL programmable delay line ■ Two (2) separate outputs; inverting & non-inverting ■ Completely interfaced


    OCR Scan     		PDU-1316F PDU-1316F-1 PDU-1316F-4 PDU-1316F-5 PDU-1316F-6 PDU-1316F-8 PDU-1316F-10 PDU-1316F-12 PDU-1316F-15 PDU-1316F-20 PDU-1316F-2 PDU-1316F-3 1316F PDF

    PDU-1364F-1

    Abstract: PDU-1364F-10 PDU-1364F-2 PDU-1364F-3 PDU-1364F-4 PDU-1364F-5 PDU-1364F-6 PDU-1364F-8 32-RK
    Text: - Digitally Programmable Delay Units PDU-1364F :L'g SERIES: 6-Bit TTL Interfaced Features: • Input & output TTL buffered ■ 6-BIT TTL programmable delay line ■ Two (2) separate outputs; inverting & non-inverting ■ Completely interfaced


    OCR Scan     		pdim364f PDU-1364F-0 PDU-1364F-1 PDU-1364F-2 PDU-1364F-3 PDU-1364F-4 PDU-1364F-5 PDU-1364F-6 PDU-1364F-8 PDU-1364F-10 32-RK PDF

    2n2222 fairchild

    Abstract: 74OL60XX
    Text: 74OL6000, 74OL6001, 74OL6010, 74OL6011 Optoplanar High-Speed Logic-to-Logic Optocouplers LSTTL to TTL Buffer TTL Inverter CMOS Buffer CMOS Inverter Description 74OL6000 74OL6001 74OL6010 74OL6011 Features • Industry first LSTTL to TTL and LSTTL to CMOS


    Original     		74OL6000, 74OL6001, 74OL6010, 74OL6011 74OL6000 74OL6001 2n2222 fairchild 74OL60XX PDF

    Untitled

    Abstract: No abstract text available
    Text: data delayW devicesYinc Digitally Programmable Delay Units SERIES: PDU-13256 8 Bit TTL Interfaced Specifications: • ■ ■ ■ ■ Features: ■ Input & output TTL buffered ■ 8-BIT TTL programmable delay line ■ Two (2) separate outputs; inverting


    OCR Scan     		PDU-13256 PDF

    ttlpd

    Abstract: 125OC TTLPD-10 TTLPD-10M TTLPD-15 TTLPD-15M TTLPD-20 TTLPD-25 TTLPD-30
    Text: TTLPD Series FAST / TTL Pulse Width Discriminator Modules Electrical Specifications at 25OC FAST / TTL Pulse Width Discriminator Modules 14-Pin Package Commercial and Mil-Grade Versions FAST/TTL Logic Buffered Pass Pulse Widths above & suppress Pulses below Nominal Value


    Original     		14-Pin TTLPD-10M TTLPD-15M TTLPD-20 TTLPD-20M TTLPD-25 TTLPD-25M TTLPD-30 TTLPD-30M TTLPD-35 ttlpd 125OC TTLPD-10 TTLPD-10M TTLPD-15 TTLPD-15M TTLPD-20 TTLPD-25 TTLPD-30 PDF

    Untitled

    Abstract: No abstract text available
    Text: Digitally Programmable Delay Units SERIES: PDU-1364F 6-Bit TTL Interfaced Features: • Input & output TTL buffered ■ 6-BIT TTL programmable delay line ■ Two (2) separate outputs; inverting & non-inverting ■ Completely Interfaced ■ Compact & low profile


    OCR Scan     		PDU-1364F PDU-1364F-0 PDU-1364F-1 PDU-1364F-2 PDU-1364F-3 PDU-1364F-4 PDU-1364F-5 PDU-1364F-6 PDU-1364F-8 PDU-1364F-10 PDF

    Untitled

    Abstract: No abstract text available
    Text: Digitally Programmable Delay Units SERIES: PDU-1364F 6-Bit TTL Interfaced Features: • Input & output TTL buffered ■ 6-BIT TTL programmable delay line ■ Two (2) separate outputs; inverting & non-inverting ■ Completely interfaced ■ Compact & low profile


    OCR Scan     		PDU-1364F PDU-1364F-1 PDU-1364F-0 PDU-1364F-2 PDU-1364F-3 PDU-1364F-4 PDU-1364F-5 PDU-1364F-6 PDU-13 PDF

    Untitled

    Abstract: No abstract text available
    Text: Digitally Programmable data \<?^V delayW Delav* Units series : PDU-1316F devicesYkic. 4-Bit TTL Interfaced Features: • Input & output TTL buffered ■ 4-BIT TTL programmable delay line ■ Two (2) separate outputs; inverting & non-inverting ■ Completely interfaced


    OCR Scan     		PDU-1316F PDU-1316F-1 PDU-1316F-45 PDU-1316F-50 PDU-1316F-60 PDU-1316F-80 PDU-1316F-100 PDF

    transistor c2026

    Abstract: c2026 transistor data 740L6000 c2028 transistor data C2036 c2026 transistor equivalent c2026 C2037 transistor C2003 740L6000 equivalent
    Text: eu HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS OPTOELECTRONICS OPTO/LOGIC TTL BUFFER TTLINVERTER CMOS BUFFER CMOS INVERTER LSTTL to \ TM ORDER INFORMATION LOGIC COMPATIBILITY PART NUMBER INPUT OUTPUT 740L6000 LSTTL TTL TTL 740L6001 LSTTL 740L6010 LSTTL CMOS 740L6011 LSTTL


    OCR Scan     		740L6000 740L6001 740L6010 740L6011 740L6011 transistor c2026 c2026 transistor data c2028 transistor data C2036 c2026 transistor equivalent c2026 C2037 transistor C2003 740L6000 equivalent PDF

    Untitled

    Abstract: No abstract text available
    Text: Digitally Programmable data delay Delay Units SERIES: PDU-1364F d evices^ 6-Bit TTL Interfaced Features: • Input & output TTL buffered ■ 6-BIT TTL programmable delay line ■ Two (2) separate outputs; inverting & non-inverting ■ Completely Interfaced


    OCR Scan     		PDU-1364F PDU-1364F-1 -1364F-0 POU-1364F-1 U-1364F-2 U-1364F-3 1364F-4 -1364F-5 U-1364F-8 1364F-10 PDF

    AI3D-12

    Abstract: AI3D-15 AI3D-20 AI3D-25 AI3D-30 AI3D-35 AI3D-10 AI3D-11
    Text: AI3D Series FAST / TTL Buffered Triple Independent Delays Electrical Specifications at 25OC 14-Pin Package Surface Mount and Thru-hole Versions Delay Tolerance ns FAST/TTL Logic Buffered 14-Pin 74F/TTL Buffered Triple Independent Delays DIP P/N G-SMD P/N


    Original     		14-Pin 74F/TTL AI3D-10 AI3D-10G AI3D-11 AI3D-11G AI3D-12 AI3D-12G AI3D-15 AI3D-12 AI3D-15 AI3D-20 AI3D-25 AI3D-30 AI3D-35 AI3D-10 AI3D-11 PDF

    ttlpwg

    Abstract: 125OC TTLPWG-10 TTLPWG-15 TTLPWG-20 TTLPWG-25 TTLPWG-30 TTLPWG-35 "FAST TTL"
    Text: TTLPWG Series FAST / TTL Pulse Width Generator Modules Electrical Specifications at 25OC 14-Pin Package Commercial and Mil-Grade Versions FAST / TTL Buffered Pulse Width Generator Modules FAST/TTL Logic Buffered Part Number Precise Pulse Width Output triggered by Rising Edge of Input


    Original     		14-Pin -55OC 125OC 150OC MIL-STD-883B 125OC. ttlpwg 125OC TTLPWG-10 TTLPWG-15 TTLPWG-20 TTLPWG-25 TTLPWG-30 TTLPWG-35 "FAST TTL" PDF

    DTZM1

    Abstract: DTZM13 125OC DTZM1-13 DTZM1-17 DTZM1-20 DTZM1-25 DTZM1-30 DTZM1-35 DTZM1-40
    Text: DTZM Series FAST / TTL Buffered 5-Tap Delay Modules Electrical Specifications at 25OC 14-Pin Package Commercial and Mil-Grade Versions TTL Buffered 5 Tap Modules FAST/TTL Logic Buffered 5 Equal Delay Taps Operating Temperature Ranges 0OC to +70OC, or -55OC to +125OC


    Original     		14-Pin -55OC 125OC DTZM1-13 DTZM1-17 DTZM1-20 DTZM1-25 DTZM1-30 DTZM1-35 DTZM1 DTZM13 125OC DTZM1-13 DTZM1-17 DTZM1-20 DTZM1-25 DTZM1-30 DTZM1-35 DTZM1-40 PDF

    SN7401

    Abstract: sn29601 SN7449 SN74298 SN74265 MC3021 SN54367 sn74142 signetics 8223 9370c
    Text: INDEX PAGE TTL Integrated Circuits Mechanical Data 1 TTL Interchangeability Guide 6 Functional Selection Guide 19 Explanation of Function Tables 38 54/74 Families of Compatible TTL Circuits 40 TTL INTEGRATED CIRCUITS MECHANICAL DATA J ceramic dual-in-line package


    OCR Scan     		24-lead SN74S474 SN54S475 SN74S475 SN54S482 SN74S482 LCC4270 SN54490 SN74490 SN54LS490 SN7401 sn29601 SN7449 SN74298 SN74265 MC3021 SN54367 sn74142 signetics 8223 9370c PDF

    PDU-13256 Series Programmable Delay Units

    Abstract: T255 TI28
    Text: data /£ \ Digitally Programmable delay Delay Units SERIES: PDU-13256 devicesVinc. (8 Bit TTL Interfaced S p e cific atio n s : • ■ ■ ■ ■ Features: ■ Input & output TTL buffered ■ 8-BIT TTL program mable delay line ■ Two (2) separate outputs; inverting


    OCR Scan     		pdu-13256 PDU-13256 Series Programmable Delay Units T255 TI28 PDF

    Untitled

    Abstract: No abstract text available
    Text: DTZM Series FASTI TTL Buffered 5-Tap Delay Modules Electrical Specifications at 25°C 14-Pin Package Commercial and Mil-Grade Versions TTL Buffered 5 Tap Modules FAST/TTL Logic Buffered 5 Equal Delay Taps Operating Temperature Ranges CPC to +7CPC, or -55°C to +125°C


    OCR Scan     		14-Pin DTZM1-13 DTZM1-17 DTZM1-100 DTZM1-125 DTZM1-150 1-20s: MIL-STD-883B PDF

    JESD22-A114-A

    Abstract: JESD78
    Text: NLU1GT50 Single Buffer, Non-Inverting, TTL Level TTL-Compatible Inputs The NLU1GT50 MiniGatet is an advanced CMOS high-speed non-inverting buffer in ultra-small footprint. The device input is compatible with TTL-type input thresholds and the output has a full 5.0 V CMOS level output swing.


    Original     		NLU1GT50 NLU1GT50 517AA 613AD 613AE 613AF NLU1GT50/D JESD22-A114-A JESD78 PDF

    Untitled

    Abstract: No abstract text available
    Text: NLU1GT50 Single Buffer, Non-Inverting, TTL Level TTL−Compatible Inputs The NLU1GT50 MiniGatet is an advanced CMOS high−speed non−inverting buffer in ultra−small footprint. The device input is compatible with TTL−type input thresholds and the output has a full 5.0 V CMOS level output swing.


    Original     		NLU1GT50 NLU1GT50 613AD 613AE 613AF 517BX 517AQ NLU1GT50/D PDF

    Untitled

    Abstract: No abstract text available
    Text: NLU1GT50 Single Buffer, Non-Inverting, TTL Level TTL−Compatible Inputs The NLU1GT50 MiniGatet is an advanced CMOS high−speed non−inverting buffer in ultra−small footprint. The device input is compatible with TTL−type input thresholds and the output has a full 5.0 V CMOS level output swing.


    Original     		NLU1GT50 517AA NLU1GT50/D PDF

    Untitled

    Abstract: No abstract text available
    Text: NLU1GT50 Single Buffer, Non-Inverting, TTL Level TTL−Compatible Inputs The NLU1GT50 MiniGatet is an advanced CMOS high−speed non−inverting buffer in ultra−small footprint. The device input is compatible with TTL−type input thresholds and the output has a full 5.0 V CMOS level output swing.


    Original     		NLU1GT50 517AA NLU1GT50/D PDF

    ic 8pin ttl

    Abstract: No abstract text available
    Text: AMDM Series FAST / TTL Buffered 5-Tap Delay Modules • Low Profile 8-Pin Package Electrical Specifications at 25°C Two Surface Mount Versions FAST/TTL 5-tap 8-Pin DIP • FAST/TTL Logic Buffered Tap Delay Tolerances +/- 5% or 2ns +/- 1ns <13ns Tap 1 Tap 2


    OCR Scan     		AMDM-11 14-Pin 74F/TTL, 100ns ic 8pin ttl PDF

    IC TTL 74LS00

    Abstract: TTL LS 7400 IC TTL 74 ls 04 7400 fan-out cmos 7400 fan-out TTL 7400 catalog TTL 74ls00 TTL 7400 rise and fall time of ic 74ls00 74LS00 gate
    Text: Design Considerations, Testing and Applications Assistance Form FAST AND LS TTL FAST AND LS TTL DATA 3-1 3 DESIGN CONSIDERATIONS SELECTING TTL LOGIC. TTL Families may be mixed in a system for optimum performance. For instance, in new designs, ALS would commonly be used in non-critical speed paths to minimize power consumption while FAST TTL would be used in high


    Original     		PDF