TSEV83102G0GL
Abstract: 10 GSPS ADC JTS83102G0 TS81102G0 TS83102G0 TS83102G0CGL
Text: Released under NDA TS83102G0 MAIN FEATURES ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! 10-bit resolution. 2 GSPS sampling rate. 3 GHz full power input bandwidth. Band flatness: ± 0.2 dB from DC up to 1.5 GHz . Very low input VSWR : 1.15 max from DC to 2GHz (packaged device).
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TS83102G0
10-bit
750MHz
52dBc
TS81102G0
TS83102G0
TSEV83102G0GL
75GHz
TSEV83102G0GL
10 GSPS ADC
JTS83102G0
TS81102G0
TS83102G0CGL
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Untitled
Abstract: No abstract text available
Text: Features • Programmable DMUX Ratio: • • • • • • • • • • • • • • – 1:4: Data Rate Max = 1 Gsps – PD 8b/10b < 4.3/4.7 W (ECL 50Ω output) – 1:8: Data Rate Max = 2 Gsps – PD (8b/10b) < 6/6.9 W (ECL 50Ω output) – 1:16 with 1 TS8388B or 1 TS83102G0 and 2 DMUX
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8b/10b)
TS8388B
TS83102G0
8-/10-bit
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porte logique
Abstract: porte logique and TS83084G0 circuit logique Transistor 8c4 TS83084G TS81102G0 TS83102G0 TS8388B TSEV8388G
Text: MAIN FEATURES ! Programmable DMUX ratio : 1:4 : Data rate max = 1 Gsps, PD 8b/10b < 4.3 / 4.7 W (ECL 50Ω output) 1:8 : Data Rate max = 2GSPS, PD (8b/10b)< 6 / 6.9 W (ECL 50Ω output) 1:16 with 1 TS8388B or 1 TS83102G0 and 2 DMUX. ! Parallel output mode.
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8b/10b
TS8388B
TS83102G0
porte logique
porte logique and
TS83084G0
circuit logique
Transistor 8c4
TS83084G
TS81102G0
TSEV8388G
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TS83084G0
Abstract: CQFP68 TS81102G0 TS83102G0 TS8388B TSEV8388G
Text: Features • Programmable DMUX Ratio: • • • • • • • • • • • • • • – 1:4: Data Rate Max = 1 Gsps – PD 8b/10b < 4.3/4.7 W (ECL 50Ω output) – 1:8: Data Rate Max = 2 Gsps – PD (8b/10b) < 6/6.9 W (ECL 50Ω output) – 1:16 with 1 TS8388B or 1 TS83102G0 and 2 DMUX
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8b/10b)
TS8388B
TS83102G0
8-/10-bit
2105B
TS83084G0
CQFP68
TS81102G0
TSEV8388G
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