TRISTATE XOR Search Results

TRISTATE XOR Result Highlights (5)

Part	Manufacturer	Description
54LS126A/BCA	Rochester Electronics LLC	54LS126 - Quad bus buffer gates with Tristate Output - Dual marked (M38510/32302BCA)
MC1230F	Rochester Electronics LLC	MC1230 - XOR Gate, ECL
MC1230L	Rochester Electronics LLC	MC1230 - XOR Gate, ECL
PAL20L10-25MJT/BV	Rochester Electronics LLC	PAL20L10 - XOR Registered 24-Pin TTL Programmable Array Logic
74F86DC	Rochester Electronics LLC	74F86 - XOR Gate, F/FAST Series, 4-Func, 2-Input, TTL, CDIP14

TRISTATE XOR Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
XC6200 Abstract: BUF C038 XC6264 xilinx XC6216 PN16 XC6209 XC6216 PW16 XC6000 N16O Text: XC6200 FPGA Family  Advanced Product Description Features • Flexible Pin Configuration - All User I/O’s programmable as in, out, bidirect, tristate or open drain. - Configurable pull-up/down resistors - CMOS or TTL logic levels - 8.32-bit CPU interface	Original	XC6200 32-bit 220MHz XC6216 -2PC84C -40oC -55oC 125oC 84-Pin TQ144 BUF C038 XC6264 xilinx XC6216 PN16 XC6209 PW16 XC6000 N16O	PDF
56MHz Abstract: 100khz quartz XOR91 Text: EURO QUARTZ XOR91 Oscillators 7 x 5mm SMD High Precision Oscillator 1.0MHz to 56.0MHz FEATURES High frequency stability 7 x 5mm SMD oscillator Femto second integrated phase jitter 300 fs typical Superior phase noise -145dBc/Hz at 100kHz offset Frequency Range 1.0MHz to 56MHz	Original	-145dBc/Hz 100kHz 56MHz XOR91 10kHz -150dBc/Hz 300fs 12kHZ 100khz quartz	PDF
56MHZ Abstract: No abstract text available Text: EURO QUARTZ XOR32 Oscillators 3.2 x 2.5mm SMD High Precision Oscillator 1.0MHz to 56.0MHz FEATURES High frequency stability 3.2 x 2.5mm SMD oscillator Femto second integrated phase jitter 300 fs typical Superior phase noise -145dBc/Hz at 100kHz offset Frequency Range 1.0MHz to 56MHz	Original	-145dBc/Hz 100kHz 56MHz XOR32 10kHz -150dBc/Hz 300fs 12kHZ	PDF
XOR53 Abstract: No abstract text available Text: EURO QUARTZ XOR53 Oscillators 5 x 3.2mm SMD High Precision Oscillator 1.0MHz to 56.0MHz FEATURES High frequency stability 5 x 3.2mm SMD oscillator Femto second integrated phase jitter 300 fs typical Superior phase noise -145dBc/Hz at 100kHz offset Frequency Range 1.0MHz to 56MHz	Original	-145dBc/Hz 100kHz 56MHz XOR53 10kHz -150dBc/Hz 300fs 12kHZ	PDF
XOR32 Abstract: No abstract text available Text: EURO QUARTZ XOR32 Oscillators 3.2 x 2.5mm SMD High Precision Oscillator 1.0MHz to 56.0MHz FEATURES High frequency stability 3.2 x 2.5mm SMD oscillator Femto second integrated phase jitter 300 fs typical Superior phase noise -145dBc/Hz at 100kHz offset Frequency Range 1.0MHz to 56MHz	Original	-145dBc/Hz 100kHz 56MHz XOR32 10kHz -150dBc/Hz 300fs 12kHZ	PDF
tristate xnor gate Abstract: tristate xor gate Tri-State Buffer CMOS SLG74LB1G99 tristate xor SLG74LB1G99V 74LVC1G99 74LVC1G99DP SN74AUP1G99 SN74LVC1G99 Text: SLG74LB1G99 GreenLIBTM ULTRA-CONFIGURABLE MULTIPLE FUNCTION GATE WITH TRI-STATE OUTPUT General Description Features The GreenLIB provides a low voltage, ultra-configurable, • Pb-Free / RoHS Compliant multiple function gate with one Tri-State Output. The device	Original	SLG74LB1G99 000-0074LB1G99-11 tristate xnor gate tristate xor gate Tri-State Buffer CMOS SLG74LB1G99 tristate xor SLG74LB1G99V 74LVC1G99 74LVC1G99DP SN74AUP1G99 SN74LVC1G99	PDF
atmel 216 Abstract: ECL IC NAND CQFP 256 PIN actel Atmel 642 PO22 tri state ATL35 atmel 334 20PCI atmel h 952 Text: Features • High-speed - 150 ps Gate Delay - 2-input NAND, FO = 2 nominal • Up to 2.7 Million Used Gates and 976 Pins • System Level Integration Technology – Cores: ARM7TDMI and AVR RISC Microcontrollers, OakDSP™ and LodeDSPCores™, 10T/100 Ethernet MAC, USB and PCI Cores	Original	10T/100 ATL35 0802E 10/99/0M atmel 216 ECL IC NAND CQFP 256 PIN actel Atmel 642 PO22 tri state atmel 334 20PCI atmel h 952	PDF
circuit diagram of Tri-State Buffer using CMOS Abstract: verilog code for UART with BIST capability block diagram for UART with BIST capability tri state AT28 vhdl code for flip-flop vhdl pid verilog code pid controller free vhdl code for usart Text: Features • 0.5 µm Drawn Gate Length 0.45 µm Leff Sea-of-Gates Architecture with • • • • • Triple-level Metal Embedded E2 Memory up to 256 Kb 3.3V Operation with 5.0V Tolerant Input and Output Buffers High-speed, 200 ps Gate Delay, 2-input NAND, FO = 2 Nominal	Original	10T/100 ATL50/E2 1173D 11/99/1M circuit diagram of Tri-State Buffer using CMOS verilog code for UART with BIST capability block diagram for UART with BIST capability tri state AT28 vhdl code for flip-flop vhdl pid verilog code pid controller free vhdl code for usart	PDF
ITE 8515 Abstract: No abstract text available Text: Features • 0.5 \|jm D raw n G ate L en gth 0.45 \|jm Leff S e a -o f-G a te s A rch ite ctu re w ith T rip le-level M etal • E m b ed d ed E2 M em o ry up to 256 Kb • 3.3 V O p e ra tio n w ith 5.0 V T o leran t Inp u t and O u tp u t B uffers • H ig h -s p e ed , 200 ps G ate Delay, 2 -in p u t N A ND, FO = 2 N o m in al	OCR Scan		PDF
verilog code for barrel shifter Abstract: 8 bit Array multiplier code in VERILOG P011F P055F 12KX 12223h Tri-State Buffer verilog code for UART with BIST capability P044V p022 Text: Features • 0.5 \|jm D raw n G ate L en gth 0.45 \|jm Leff S e a -o f-G a te s A rch ite ctu re w ith T rip le-level M etal • E m b ed d ed E2 M em o ry up to 256 Kb • 3.3 V O p e ra tio n w ith 5.0 V T o leran t Inp u t and O u tp u t B uffers • H ig h -s p e ed , 200 ps G ate Delay, 2 -in p u t N A ND, FO = 2 N o m in al	OCR Scan	10T/100 ATL50/E2 verilog code for barrel shifter 8 bit Array multiplier code in VERILOG P011F P055F 12KX 12223h Tri-State Buffer verilog code for UART with BIST capability P044V p022	PDF
TEMIC PLD Abstract: PRU10 PRD8 buffer 8x Structure of D flip-flop DFFSR AOI222 AOI2223 AOI2223H AOI222H MH1099 Text: MH1 1.6 Million gates Sea of Gates / Embedded Arrays 1. Description The MH1 Series Gate Array and Embedded Array families from TEMIC are fabricated in a 0.35µ CMOS process, with up to 3 levels of metal. This family features arrays with up to 1.6 million routable gates and 600 pins. The	Original		PDF
Transistor Equivalent list po55 Abstract: Structure of D flip-flop DFFSR tristate buffer sis 968 PO-44Z PRU11 AC/DC drive nec 78054 PO22 tristate buffer cmos Text: Features • High Speed - 180 ps Gate Delay - 2 input NAND, FO=2 nominal • Up to 1.198 M Used Gates and 512 Pads with 3.3 V, 3V and 2.5V libraries when tested to space quality grades • Up to 1.6M Used Gates and 596 Pads with 3.3 V, 3V and 2.5V libraries when tested to	Original		PDF
AVR 8515 microcontroller Abstract: FPGA AMI coding decoding tri state AOI222 AOI2223 AOI2223H AOI222H ATL35 0.35-um CMOS standard cell library inverter Text: Features • System Level Integration Technology • 0.35 µm Geometry in Triple-level Metal • I/O Interfaces; CMOS, LVTTL, LVDS, PCI, USB – Output Currents up to 20 mA, 5V Tolerant I/O • Embedded Flash Memory with Capacities of 1Mbit, 2Mbit or 4Mbit	Original	22-bit 16-bit 1184B 03/00/xM AVR 8515 microcontroller FPGA AMI coding decoding tri state AOI222 AOI2223 AOI2223H AOI222H ATL35 0.35-um CMOS standard cell library inverter	PDF
tristate buffer Abstract: smd transistor AO HEX TO DECIMAL tristate buffer cmos A101 A201 MH1099E MH1156E PO11F MH1332E Text: Features • High Speed - 180 ps Gate Delay - 2 Input NAND, FO = 2 nominal • Up to 1.198M Used Gates and 512 Pads with 3.3V, 3V and 2.5V Libraries when Tested to Space Quality Grades • Up to 1.6M Used Gates and 596 Pads with 3.3V, 3V and 2.5V Libraries when Tested to	Original	4110F tristate buffer smd transistor AO HEX TO DECIMAL tristate buffer cmos A101 A201 MH1099E MH1156E PO11F MH1332E	PDF

AOI222 Abstract: AOI2223 AOI222H MH1099 MH1242 0.35-um CMOS standard cell library inverter Text: Features • High Speed - 170 ps Gate Delay - 2 Input NAND, FO = 2 Nominal • Up to 1.6 Million Used Gates and 596 Pads, with 3.3V, 3V, and 2.5V Libraries • System Level Integration Technology Cores on Request: SRAM and TRAM (Gate Level or Embedded) • I/O Interfaces:	Original	5962-01B01 4138E AOI222 AOI2223 AOI222H MH1099 MH1242 0.35-um CMOS standard cell library inverter	PDF
16-LINE TO 4-LINE PRIORITY ENCODERS Abstract: 32-Bit Parallel-IN Serial-OUT Shift Register RS flip flop cmos 16-to-4 line priority encoder RS flip flop DSTD190 CMOS Quad 2-Input NOR Gate encoder 74174 jk flip flop to d flip flop conversion T Flip-Flop Text: CMOS PLD Designing with the Atmel-ViewPLD Development Tool Like the Atmel-ABEL software, the Atmel-ViewPLD development tool uses a popular industry-standard CAE development system. The development tool integrates the Viewlogic Workview software as the design environment with Data I/O’s	Original	thD882 32-Bit DSTD90 DSTD91 DSTD92 Divide-by-12 DSTD93 DSTD94 ATV5000 ATV5100 16-LINE TO 4-LINE PRIORITY ENCODERS 32-Bit Parallel-IN Serial-OUT Shift Register RS flip flop cmos 16-to-4 line priority encoder RS flip flop DSTD190 CMOS Quad 2-Input NOR Gate encoder 74174 jk flip flop to d flip flop conversion T Flip-Flop	PDF
TGMR Abstract: PT80 T-type flip flop Text: 8000 Family Architectural Description Outputs from the GLBs in a Big Fast Megablock can drive both the Big Fast Megablock Routing Pool within the Big Fast Megablock and the Global Routing Plane between the Big Fast Megablocks. Switching resources are provided to allow signals in the Global Routing Plane to drive	Original		PDF
Untitled Abstract: No abstract text available Text: 8000 and 8000V Family Architectural Description Outputs from the GLBs in a Big Fast Megablock can drive both the Big Fast Megablock Routing Pool within the Big Fast Megablock and the Global Routing Plane between the Big Fast Megablocks. Switching resources are provided to allow signals in the Global Routing Plane to drive	Original		PDF
PT80 Abstract: No abstract text available Text: 8000 and 8000V Family Architectural Description Outputs from the GLBs in a Big Fast Megablock can drive both the Big Fast Megablock Routing Pool within the Big Fast Megablock and the Global Routing Plane between the Big Fast Megablocks. Switching resources are provided to allow signals in the Global Routing Plane to drive	Original		PDF
8000 Families Abstract: PT80 Text: ispLSI 8000 and 8000V Family Architectural Description October 2001 Introduction The ispLSI 8000 and 8000V Family of Register-Intensive, SuperBIG In-System Programmable Logic Devices is based on Big Fast Megablocks of 120 registered macrocells and a Global Routing Plane GRP structure interconnecting the Big Fast Megablocks. Each Big Fast Megablock contains 120 registered macrocells arranged in six	Original		PDF
PO61 Abstract: ATMEL 340 atmel 424 ATLS60 ATL60 ttl buffer 3.6v Tri-State Buffer bga ambit inverter circuit AOI222 ATMEL 218 Text: Features • • • • • • • • 0.6 µm Drawn Gate Length 0.5 µm Leff Sea-of-Gates Architecture with Triple Level Metal 5.0V, 3.3V and 2.0V Operation including Mixed Voltages On-chip Phase Locked Loop Available to Synthesize Frequencies up to 150 MHz and	Original	ATL60 0388C 11/99/xM PO61 ATMEL 340 atmel 424 ATLS60 ttl buffer 3.6v Tri-State Buffer bga ambit inverter circuit AOI222 ATMEL 218	PDF
Peripheral interface 8255 with ADC Abstract: ttl XOR gate circuit 8255 peripheral interface 8051 8255 programmable peripheral interface 8254 with 8051 Nand gate Crystal Oscillator atmel sd controller 7816 Peripheral interface 8255 with microcontroller OSC27M adc8 8 bit converter Text: Library Cell Index April 1997 DSP and Microcontroller Cores Code Description OakDSPCoreTM 16-bit DSP core ARM7TDMITM ARM7 Thumb 32-bit RISC microcontroller core ARM7DMITM ARM7 32-bit RISC microcontroller core AVRTM 8-bit RISC microcontroller core CB_8032 8-bit microcontroller core	Original	16-bit 32-bit PC45x Peripheral interface 8255 with ADC ttl XOR gate circuit 8255 peripheral interface 8051 8255 programmable peripheral interface 8254 with 8051 Nand gate Crystal Oscillator atmel sd controller 7816 Peripheral interface 8255 with microcontroller OSC27M adc8 8 bit converter	PDF
2 bit magnitude comparator Abstract: dece2x4 TA194 TA688 4 bit identity comparator AO11 TA164 2-bit down counter TA161 DLM8 Text: Accelerator Series Macro Library – Tables of Hard, Soft, and TTL Macros Hard Macros—Combinatorial Modules Function Macro Description Combinatorial Logic Module CM8 Combinational Module Full ACT 3 Logic Module Sequential Logic Module DFM8A 4-bit D-Type Flip-Flop with Multiplexed Data, active low Clear, and active	Original	TA269 TA273 TA280 TA377 TA688 2 bit magnitude comparator dece2x4 TA194 TA688 4 bit identity comparator AO11 TA164 2-bit down counter TA161 DLM8	PDF
z63n Abstract: t28000 z65n 07in M6008 mitsubishi lable fr1s MITSUBISHI GATE ARRAY z66n R12W Text: A m itsu b ish i ELECTRO N IC DEVICE GROUP P R E LIM IN A R Y M6008X 0.8 Jim CMOS GATE ARRAYS Mitsubishi M6008X Series 0.8 Jim CMOS Gate Arrays INTRODUCTION Mitsubishi offers sub-m icron CMOS Gate Arrays us ing a 0.8 micron drawn twin well silicon gate process	OCR Scan	M6008X MDS-GA-02-03-91 z63n t28000 z65n 07in M6008 mitsubishi lable fr1s MITSUBISHI GATE ARRAY z66n R12W	PDF

TRISTATE XOR Search Results

TRISTATE XOR Result Highlights (5)

TRISTATE XOR Datasheets Context Search

XC6200

56MHz

56MHZ

XOR53

XOR32

tristate xnor gate

atmel 216

circuit diagram of Tri-State Buffer using CMOS

ITE 8515

verilog code for barrel shifter

TEMIC PLD

Transistor Equivalent list po55

AVR 8515 microcontroller

tristate buffer

AOI222

16-LINE TO 4-LINE PRIORITY ENCODERS

TGMR

Untitled

PT80

8000 Families

PO61

Peripheral interface 8255 with ADC

2 bit magnitude comparator

z63n