TPLH11 Search Results

Contextual Info: SN74ALS235 64 x 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY _ SQAS108A - OCTOBER 1986 - REVISED SEPTEMBER 1993 • • • • • Asynchronous Operation Organized as 64 Words by 5 Bits Data Rates From 0 to 25 MHz 3-State Outputs

CDCLVP2106

Abstract: QFN-40 weight
Contextual Info: CDCLVP2106 www.ti.com. SCAS887 – SEPTEMBER 2009 12 LVPECL Output, High-Performance Clock Buffer

CDC337

Abstract: CDC337DBLE CDC337DW CDC337DWG4 CDC337DWR CDC337DWRG4 CDC337NS MS-013
Contextual Info: CDC337 CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS330B – DECEMBER 1990 – REVISED OCTOBER 1998 D D D D D D D DW PACKAGE TOP VIEW Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications TTL-Compatible Inputs and CMOS-Compatible Outputs

SCANSTA111

Abstract: STA111
Contextual Info: SCANSTA111 Enhanced SCAN bridge Multidrop Addressable IEEE 1149.1 JTAG Port General Description The SCANSTA111 extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The advantage of a multidrop approach over a single serial scan chain is improved test throughput and the ability to remove a board

CDC318

Contextual Info: CDC318 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS587B – JANUARY 1997 – REVISED MARCH 1998 D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps

c.i 9409

Contextual Info: CDC339 CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS331 – DECEMBER 1992 – REVISED MARCH 1994 D D D D D D D DB OR DW PACKAGE TOP VIEW Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications TTL-Compatible Inputs and Outputs Distributes One Clock Input to Eight

UT54AC

Contextual Info: Standard Products UT54ACTS899 RadHard 9-bit Latchable Transceiver with Parity Generator/Checker Datasheet March 14, 2007 www.aeroflex.com/radhard FEATURES PIN DESCRIPTION ‰ Latchable transceiver with output source/sink of 24mA ‰ Option to select generate parity and check or "feed-through"

SWBT13

Abstract: rta2 1553b rti
Contextual Info: UT1553B BCRT p Register-oriented architecture to enhance FEATURES p Comprehensive MIL-STD-1553B dual-redundant programmability p DMA memory interface with 64K addressability p Internal self-test p Remote terminal operations in ASD/ENASD-certified Bus Controller BC and Remote Terminal

fp6160

Abstract: rta2
Contextual Info: UT1553B BCRT p Register-oriented architecture to enhance FEATURES p Comprehensive MIL-STD-1553B dual-redundant programmability p DMA memory interface with 64K addressability p Internal self-test p Remote terminal operations in ASD/ENASD-certified Bus Controller BC and Remote Terminal

Contextual Info: 3.3 V CMOS 18-BIT REGISTER 3-STATE , 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: - IDT74LVC16823A ADVANCE INFORMATION The LVC16823A18-bit edge-triggered D-type register is built using advanced dual metal CMOS technology.This high-speed, low-power register is ideal for use as a buffer register for data

Contextual Info: FAST CMOS BUFFER/CLOCK DRIVER IDT49FCT3805/A Integrated Device Technology, Inc. FEATURES: DESCRIPTION: 0 .5 M IC R O N C M O S Technology T h e F C T 3 8 0 5 /A is a 3 .3 volt, non-inverting clock driver built G u aranteed low skew < 500p s m ax. using advanced dual m etal C M O S technology. T h e device

Contextual Info: IDT74LVCH32373A 3.3V CMOS 32-BIT ADVANCE TRANSPARENT D-TYPE LATCH INFORMATION WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD DESCRIPTION: FEATURES: - Typical tS K o (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)

Contextual Info: IDT74FCT3807/A 3.3V CMOS 1-TO-10 CLOCK DRIVER In te g rate d D ev ice T ech n ology , Inc. FEATURES: DESCRIPTION: • 0 .5 M IC R O N C M O S Technology • G u aran teed low skew < 3 5 0 p s m ax. • V ery low duty cycle distortion < 3 5 0p s (m ax.) •

Contextual Info: FAST CMOS BUFFER/CLOCK DRIVER IDT54/74FCT81OBT/CT Integrated Device Technology, Inc. FEATURES: • • 0.5 MICRON CM OS technology • Guaranteed low skew < 600ps max. packages Military product compliant to MIL-STD-883, Class B DESCRIPTION: • Very low duty cycle distortion < 700ps (max.)

Contextual Info: CDC337 CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS330B – DECEMBER 1990 – REVISED OCTOBER 1998 D D D D D D D DW PACKAGE TOP VIEW Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications TTL-Compatible Inputs and CMOS-Compatible Outputs

80c85

Abstract: HS80C85
Contextual Info: S H S - 5 4 C 1 3 8 R H R a d ia t io n H a r d e n e d February 1996 3 - L in e to 8 - L in e D e c o d e r /D e m u lt ip le x e r Features Pinouts • Devices QML Qualified in Accordance With MIL-PRF-38535 16 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE SBDIP

LVC139A

Abstract: DSC-4720
Contextual Info: IDT74LVC139A 3.3V CMOS DUAL ADVANCE INFORMATION 2-LINE TO 4-LINE DECODER/DEMULTIPLEXER, 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: - 0.5 M IC R O N C M O S T e c h n o lo g y ESD > 2 0 0 0 V p e r M IL -S T D -8 8 3 , M e th o d 3 0 1 5 ; > 2 0 0 V using m a c h in e m o d e l C = 2 0 0 p F , R = 0

Contextual Info: 3.3V CMOS TRIPLE 3-INPUT AND GATE, 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: - 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0 1.27mm pitch SOIC, 0.65mm pitch SSOP and 0.65mm pitch TSSOP packages

Contextual Info: PCI CONTROLLER PLL CLOCK DRIVER FEATURES: - 10 Clock Outputs configured in 3 groups Internal loop filter 5V tolerant inputs Output enable O E PLL lock indicator output Extended -40 to 85°C operation Low skew guaranteed between outputs Sense control input

Contextual Info: 3.3V CMOS QUADRUPLE 2-LINE TO 1-LINE DATA IDT74LVC258A ADVANCE INFORMATION SELECTOR/MULTIPLEXER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O FEATURES: - DESCRIPTION: 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0

Contextual Info: 3.3V CMOS 1-TO-10 CLOCK DRIVER IDT74FCT3807/A Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • • • • • • • • • • • • • The FCT3807/A 3.3V clock driver is built using advanced dual metal CMOS technology. This low skew clock driver

ZY17

Contextual Info: 3.3V CMOS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS FEATURES: - IDT74ALVC16834 DESCRIPTION: This 18-bit universal bus driver is built using advanced dual metal CMOS technology. Data flow from A to Y is con­ trolled by the output-enable OE . The device operates in

Contextual Info: 3.3V CMOS QUADRUPLE 2-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER WITH 3-STATE OUTPUTS, 5V TOLERANT I/O FEATURES: - 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0 1,27mm pitch SOIC, 0.635mm pitch QSOP,

Contextual Info: h N æ FAST C M O S IDT54/74FCT807BT/CT 1 -T O -1 0 C L O C K D R IV E R ¡ r y In tegrated D ev:be Tech n ology, l i e . FEATURES: • • • • • • • • • • • • > 200V using machine model C = 200pF, R = 0 • Available in DIP, SOIC, SSOP, QSOP, Cerpackand