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    THRESHOLD DEVICE IN VHDL Search Results

    THRESHOLD DEVICE IN VHDL Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    BLM15PX121BH1D Murata Manufacturing Co Ltd FB SMD 0402inch 120ohm POWRTRN Visit Murata Manufacturing Co Ltd
    BLM15PX181SH1D Murata Manufacturing Co Ltd FB SMD 0402inch 180ohm POWRTRN Visit Murata Manufacturing Co Ltd
    BLM21HE802SN1L Murata Manufacturing Co Ltd FB SMD 0805inch 8000ohm NONAUTO Visit Murata Manufacturing Co Ltd
    BLM15PX330BH1D Murata Manufacturing Co Ltd FB SMD 0402inch 33ohm POWRTRN Visit Murata Manufacturing Co Ltd
    BLM15PX600SH1D Murata Manufacturing Co Ltd FB SMD 0402inch 60ohm POWRTRN Visit Murata Manufacturing Co Ltd

    THRESHOLD DEVICE IN VHDL Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    M25PXX

    Abstract: spi flash m25pxx M25PXX-VHDL vhdl spi bus M25P M25P20 eeprom st generic SPI M25P10 vhdl uses
    Text: M25PXX-VHDL USER MANUAL M25Pxx Serial Flash Memory VHDL Model, V1.0 WARNING: These VHDL models are provided “as is” without warranty of any kind, including, but not limited to, any implied warranty of merchantability and fitness for a particular purpose.


    Original     		M25PXX-VHDL M25Pxx M25Pxx spi flash m25pxx M25PXX-VHDL vhdl spi bus M25P M25P20 eeprom st generic SPI M25P10 vhdl uses PDF

    atmel 718

    Abstract: ATA6662 lin transceiver ATA6663 VHDL VHDL-AMS
    Text: VHDL-AMS Behavioral Model Description 1. Introduction ATA6662 This document provides an overview of VHDL-AMS behavioral model of the LIN transceiver ATA6662. The models have been written in VHDL-AMS for use with the simulation tools AdvanceMS 4.1_1.1 and SystemVision 5.0. Test have been performed on Sun Sparc


    Original     		ATA6662 ATA6662. 9131B atmel 718 ATA6662 lin transceiver ATA6663 VHDL VHDL-AMS PDF

    atmel 718

    Abstract: ATA6663 ata6662c ATA6662 ATA6664 ata666x Behavioral verilog model
    Text: Functional VHDL-AMS Model Description 1. Introduction This documentation provides an overview of the functional VHDL-AMS model of the Atmel LIN transceivers ATA6662, ATA6662C, ATA6663, and ATA6664. The LIN transceivers have nearly the same behavior, the slight differences are described in an


    Original     		ATA6662, ATA6662C, ATA6663, ATA6664. ATA6662 ATA6662C ATA6663 ATA6664 9205B ATA666x atmel 718 ATA6663 ata6662c ATA6662 ATA6664 ata666x Behavioral verilog model PDF

    FPGA XILINX spartan3 dtc

    Abstract: mpeg 4 encoder interface of camera with virtex 5 fpga for image vhdl coding for sram 8x8 DS511 xilinx asynchronous fifo
    Text: - THIS IS A DISCONTINUED IP CORE - MPEG-4 Simple Profile Encoder v1.2 DS511 v1.8 April 14, 2008 Product Specification Introduction The Xilinx MPEG-4 Part 2 Simple Profile Encoder MPEG-4 Encoder core is a fully functional VHDL design implemented on a Xilinx FPGA. The MPEG-4


    Original     		DS511 FPGA XILINX spartan3 dtc mpeg 4 encoder interface of camera with virtex 5 fpga for image vhdl coding for sram 8x8 xilinx asynchronous fifo PDF

    Untitled

    Abstract: No abstract text available
    Text: POS-PHY Level-3 PHY Layer Core March 29, 2002 Product Specification LogiCORE Facts Core Specifics Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax: +1 408-559-7114 E-mail: logicore@xilinx.com URL: www.xilinx.com/ipcenter Support: www.support.xilinx.com


    Original     		PDF

    asynchronous fifo vhdl

    Abstract: No abstract text available
    Text: POS-PHY Level-3 Link Layer Core V1.0 March 29, 2002 Product Specification LogiCORE Facts Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax: +1 408-559-7114 E-mail: logicore@xilinx.com URL: www.xilinx.com/ipcenter Support: www.support.xilinx.com


    Original     		sml16 asynchronous fifo vhdl PDF

    22V10

    Abstract: 22V10A LVCMOS25 LVCMOS33 ABEL plastron
    Text: Using the ispGAL22V10A in the QFN Package November 2007 Application Note AN8074 Introduction Lattice’s ispGAL 22V10A device in the QFN package provides several added capabilities to the standard 22V10 architecture. The QFN Quad Flat pack, No lead package, also known as the MLF (Micro Lead Frame) package, is


    Original     		ispGAL22V10A AN8074 22V10A 22V10 1800adapter 1-800-LATTICE 22V10 LVCMOS25 LVCMOS33 ABEL plastron PDF

    ne 5555 timer

    Abstract: EIA96 emmc spec "Power Management ICs" POWR1220AT8 powr607 200w computer power supply Circuit diagram block diagram of dual 12v power supply emmc 4.5 medical ultrasound guide
    Text: Power 2 You A Guide to Power Supply Management and Control Board Power Management Functions LEARN HOW TO: »» Reduce Power Management Costs »» Increase System Reliability »» Reduce the Risk of Circuit Board Respins Shyam Chandra Power 2 You A Guide to Power Supply


    Original     		B0041 ne 5555 timer EIA96 emmc spec "Power Management ICs" POWR1220AT8 powr607 200w computer power supply Circuit diagram block diagram of dual 12v power supply emmc 4.5 medical ultrasound guide PDF

    22V10A

    Abstract: LVCMOS33 LVCMOS18 QFN PACKAGE thermal resistance LVCMOS25 QFN footprint amkor mlf qfn
    Text: Using the ispGAL22V10A in the QFN Package April 2003 Application Note AN8074 Introduction Lattice’s ispGAL 22V10A device in the QFN package provides several added capabilities to the standard 22V10 architecture. The QFN Quad Flat pack, No lead package, also known as the MLF (Micro Lead Frame) package, is


    Original     		ispGAL22V10A AN8074 22V10A 22V10 sizCMOS25 LVCMOS18 ispGAL22V10A 1800adapter 1-800-LATTICE LVCMOS33 QFN PACKAGE thermal resistance LVCMOS25 QFN footprint amkor mlf qfn PDF

    EP2C15AF484C6

    Abstract: EP3C5F256C6 EP3SL50F484C2 PDN0906 ep3sl70f484 EP2C5F256C6 OC48 PM5351 PM7325
    Text: POS-PHY Level 2 and 3 Compiler User Guide c The IP described in this document is scheduled for product obsolescence and discontinued support as described in PDN0906. Therefore, Altera does not recommend use of this IP in new designs. For more information about Altera’s


    Original     		PDN0906. EP2C15AF484C6 EP3C5F256C6 EP3SL50F484C2 PDN0906 ep3sl70f484 EP2C5F256C6 OC48 PM5351 PM7325 PDF

    fifo vhdl

    Abstract: POS-PHY pmc OC48 PM5351 PM7325 ep1m20 vhdl code for phy interface
    Text: POS-PHY Level 2 & 3 Compiler MegaCore Functions April 2001 User Guide v0.5.0 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com A-UG-POS-PHY_COMP-0.5.0 POS-PHY Level 2 & 3 Compiler MegaCore Functions User Guide Altera, ACEX, APEX, APEX 20K, MegaCore, MegaWizard, Mercury, OpenCore, Quartus and Quartus II are trademarks and/or


    Original     		PDF

    Untitled

    Abstract: No abstract text available
    Text: Digital Video Broadcasting - Asynchronous Serial Interface DVB-ASI  IP Core User’s Guide December 2010 IPUG90_01.1 Table of Contents Chapter 1. Introduction . 4


    Original     		IPUG90 PDF

    digital FIR Filter VHDL code

    Abstract: verilog code for interpolation filter code iir filter in vhdl verilog code for decimation filter digital FIR Filter verilog code application circuit for FIR filter matlaB design FIR filter matlaB design FIR Filter verilog code 00D8 EP3C16F484C6
    Text: FIR Compiler II MegaCore Function User Guide FIR Compiler II MegaCore Function User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com UG-01072-2.0 Document last updated for Altera Complete Design Suite version: Document publication date: 10.0 July 2010


    Original     		UG-01072-2 digital FIR Filter VHDL code verilog code for interpolation filter code iir filter in vhdl verilog code for decimation filter digital FIR Filter verilog code application circuit for FIR filter matlaB design FIR filter matlaB design FIR Filter verilog code 00D8 EP3C16F484C6 PDF

    32x32 multiplier verilog code

    Abstract: No abstract text available
    Text: Prelim inary Advance inform ation Actel’s Reprogrammable SPGAs General Description Features SRAM-based System Programmable Gate Array SPGA Efficient silicon target for reusable VHDL and Verilog defined soft blocks Fine-grained logic and routing architecture


    OCR Scan     		A65ES100 32x32 multiplier verilog code PDF

    Untitled

    Abstract: No abstract text available
    Text: 2D Edge Detector IP Core User’s Guide February 2011 IPUG86_01.0 Table of Contents Chapter 1. Introduction . 3 Quick Facts . 3


    Original     		IPUG86 720x480 1280x720 LFXP2-40E-6F672Cdevice PDF

    mpeg 4 encoder

    Abstract: video encoder mpeg DS511 interface of camera with virtex 5 fpga for image mpeg4 vhdl code for spartan 6 audio
    Text: MPEG-4 Simple Profile Encoder v1.1 DS511 v1.7.1 December 15, 2006 Product Specification Introduction The Xilinx MPEG-4 Part 2 Simple Profile Encoder (MPEG-4 Encoder) core is a fully functional VHDL design implemented on a Xilinx FPGA. The MPEG-4 Encoder core accepts uncompressed video and generates compressed bit streams based on the “Information


    Original     		DS511 DSP48s Mults/DSP48s" mpeg 4 encoder video encoder mpeg DS511 interface of camera with virtex 5 fpga for image mpeg4 vhdl code for spartan 6 audio PDF

    ds2 lio board

    Abstract: rt256 PCLX PQ208 PQ240 16*16 array multiplier VERILOG
    Text: tt Prelim inary A d van ce In fo rm atio n n ÆÈfiGlm '•■■ 1 ' * Actel’s Reprogrammable SPGAs F e a tu re s • SRAM-based System SPGA G e n e r a l D e s c r ip tio n Programmable Gate Array • Efficient silicon target for reusable VHDL and Verilog


    OCR Scan     		A65ES100 ds2 lio board rt256 PCLX PQ208 PQ240 16*16 array multiplier VERILOG PDF

    MUSBFDRC

    Abstract: verilog code for amba ahb bus Mentor inventra USB Full-Speed Dual-Role Controller "USB" peripheral
    Text: Inventra MUSBFDRC USB Full-Speed Dual-Role Controller Soft Core RTL IP D A T A S H E E T Endpoint Control EP0 Control - Host EP0 Control - Function EP1 - 15 Control DMA Requests Transmit IN Receive IN Host Transaction Scheduler Combine Endpoints CPU Interface


    Original     		PD-40134 005-FO MUSBFDRC verilog code for amba ahb bus Mentor inventra USB Full-Speed Dual-Role Controller "USB" peripheral PDF

    atmel h 208

    Abstract: No abstract text available
    Text: A TL Features * 1.0 |i Drawn Gate Length High-performance CMOS Gate Arrays * All ATL Gate Arrays are Specified from 3.0 Volts to 5.5 Volts, for Standard and Low Voltage Applications * Design Translation of Existing ASIC Designs Provide for Easy Alternate Sourcing with Equivalent or Improved Performance


    OCR Scan     		MIL-STD-883 MIL-STD-883 atmel h 208 PDF

    vhdl code 16 bit LFSR

    Abstract: vhdl code 8 bit LFSR vhdl code 4 bit LFSR vhdl code 10 bit LFSR vhdl code 16 bit LFSR with VHDL simulation output verilog code 8 bit LFSR verilog code 16 bit LFSR verilog code 32 bit LFSR verilog code 5 bit LFSR pseudo random generator
    Text: Channel January 10, 2000 Product Specification AllianceCORE Facts CSELT S.p.A Via G. Reiss Romoli, 274 I-10148 Torino, Italy Phone: +39 011 228 7165 Fax: +39 011 228 7003 E-mail: viplibrary@cselt.it URL: www.cselt.it Features • Supports Spartan, Spartan™-II, Virtex™, and


    Original     		I-10148 vhdl code 16 bit LFSR vhdl code 8 bit LFSR vhdl code 4 bit LFSR vhdl code 10 bit LFSR vhdl code 16 bit LFSR with VHDL simulation output verilog code 8 bit LFSR verilog code 16 bit LFSR verilog code 32 bit LFSR verilog code 5 bit LFSR pseudo random generator PDF

    Marvell 88E1111 vhdl

    Abstract: marvell 88e1145 88E1111 PHY registers map Triple-Speed Ethernet M DM7041 Marvell PHY 88E1111 finisar 5SGXM DP83865 88E1111 stratix iii MDIO clause 22 5SGXMA 88E1145 registers
    Text: Triple-Speed Ethernet MegaCore Function User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com Software Version: Document Date: 11.1 November 2011 Copyright 2011 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other


    Original     		PDF

    uart vhdl

    Abstract: XC5VLX50-FF676
    Text: LogiCORE IP XPS SYSMON ADC v3.00.b DS620 October 19, 2011 Product Specification Introduction LogiCORE IP Facts Table The Xilinx Platform Studio (XPS) System Monitor (SYSMON) Analog-to-Digital Converter (ADC) Intellectual Property (IP) core is a 32-bit slave


    Original     		DS620 32-bit uart vhdl XC5VLX50-FF676 PDF

    amd c-50

    Abstract: ATL100 ATL10C ATL130 ATL15C ATL160 ATL20 ATL20C ATL40 ATL60
    Text: ATL Features • 1.0 ji Drawn Gate Length High-performance CMOS Gate Arrays • All ATL Gate Arrays are Specified from 3.0 Volts to 5.5 Volts, for Standard and Low Voltage Applications • Design Translation of Existing ASIC Designs Provide for Easy Alternate Sourcing with Equivalent or Improved Performance


    OCR Scan     		MIL-STD-883 0Q73CI3 amd c-50 ATL100 ATL10C ATL130 ATL15C ATL160 ATL20 ATL20C ATL40 ATL60 PDF

    Untitled

    Abstract: No abstract text available
    Text: SP5301 SIGNAL PROCESSING EXCELLENCE Universal Serial Bus Transceiver • Utilizes digital inputs and outputs to transmit and receive USB cable data ■ Supports 12Mbps "Full Speed" and 1.5Mbps "Low Speed” serial data transmission ■ Compatible with the VHDL "Serial


    OCR Scan     		SP5301 12Mbps PDIUSBP11 SP5301 SP5301DS/09 PDF