TEXAS INSTRUMENT N PACKAGE Search Results

Contextual Info: SN74ALS679 12-BIT ADDRESS COMPARATORS D2M 1, JU N E 1982 - REVISED MAY1986 • Dependable Texas Instrument* Quality and Reliability 8N 74A LM 79 OW OR N PACKAGE ITO P VIEW I A 1[ 1 U A2 C 2 A3 C 3 A* C 4 A S[ 5 A 0[ 6 description The 'ALS679 address comparators simplify

LG TV 29 PCB circuits DIAGRAM

Abstract: SCAS113 74AC11132
Contextual Info: TEXAS INSTR LO fi lC 2SE C • 6U1723 0004733 8 ■ 54AC11132,74AC11132 QUADRUPLE 2-INPUT POSITIVE-NAND SCHMITT-TRIGGERS SCAS113 - D3482, MARCH 1990 Operation From Very Slow Input Transitions 54ACT1132. . . J PACKAGE 74AC11132. . . D OR N PACKAGE (TOP VIEW)

peripheral driver

Contextual Info: I | SN75439 QUADRUPLE PERIPHERAL DRIVER S L R S 0 1 3 A - MAY 1988 - REVISED NOVEM BER 1989 NE PACKAGE TOP VIEW • 1.3-A Current Capability Each Channel • Saturating Outputs With Low On-State Resistance • Two Inverting and TVvo Noninverting Driver Channels With Common Active-Low Enable

TI0103

Contextual Info: 54ACT11112, 74ACT11112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET T I0103— D 3339, JUNE 1989— REVISED JAN U AR Y 1990 • Inputs are TTL-Voltage Compatible 54ACT11112 . . . J PACKAGE 74ACT11112 . . . D OR N PACKAGE Flow-Through Architecture to Optimize PCB

Contextual Info: SN54ABT16540, SN74ABT16540A 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS206C - FEBRUARY 1991 - REVISED APRIL 1997 Members of the Texas Instruments Widebus Family State-of-the-Art EP/C-II0™ BiCMOS Design Significantly Reduces Power Dissipation SN54ABT16540 . . . WD PACKAGE

54AC11379

Abstract: 54ACT11379 74AC11379 74ACT11379 D3414
Contextual Info: 54AC11379, 74AC11379 QUAD D-TYPE FLIP-FLOPS WITH CLOCK ENABLE TI0143— D3414, MAHCH 1990 Clock Enable Latched to Avoid False Clocking 54AC11379 . . . J PACKAGE 74AC11379 . . . DW OR N PACKAGE <TOP VIEW Applications Include: Buffer/Storage Registers, Shift Registers, Pattern

54AC11379

Abstract: 54ACT11379 74AC11379 74ACT11379 d3414
Contextual Info: 54AC11379, 74AC11379 QUAD D-TYPE FLIP-FLOPS WITH CLOCK ENABLE TI0143— D3414, MAHCH 1990 Clock Enable Latched to Avoid False Clocking 54AC11379 . . . J PACKAGE 74AC11379 . . . DW OR N PACKAGE <TOP VIEW Applications Include: Buffer/Storage Registers, Shift Registers, Pattern

D3460

Contextual Info: 54ACT11208, 74ACT11208 DUAL 1-LINE TO 4-LINE CLOCK DRIVERS WITH 3-STATE OUTPUTS T I 0 1 9 8 — D 3 4 6 0 , A P R IL 1 9 9 0 54ACT11208 . . . J PACKAGE 74ACT11208 . . . D W O R N PACKAGE Inputs are TT L-V o ltag e Com patible Lo w Skew P ropagation D elay Specifications

RS-2019

Abstract: TI0112 74ACT11194 54ACT11194 1734D
Contextual Info: 54ACT11194, 74ACT11194 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS TI0112— D 3391, NOVEMBER 1989 Inputs are TTL-Voltage Compatible 54ACT11194 . . . J PACKAGE 74ACT11194 . . . DW OR N PACKAGE Parallel-to-Serial, Serial-to-Parallel Conversions TOP VIEW

c2235

Abstract: 74ACT16841 D3548 ci-42 TI0272-D3548
Contextual Info: SN54AC/ACT16841, SN74AC/ACT16841 20-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS TI0272—03548, JUNE 1990 Members of Texas Instruments Widebus Family 74AC/ACT16341 . . . DL PACKAGE 54AC/ACT16841 . . . WD PACKAGE TOP VIEW Packaged In Shrink Small-Outline 300-mll

u2d1

Abstract: 65630 54AC16824 54ACT16824 74AC16824 74ACT16824
Contextual Info: 54AC16824, 54ACT16824 74AC16824, 74ACT16824 18-BIT D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS _ TI0255— D3578, JUNE 1990 Members of Texas Instruments Widebus Family 54AC16824, 54ACT16824 . . . W D PACKAGE 74AC16824, 74ACT16824 . . . DL PACKAGE TOP VIEW

H1A1

Abstract: 54ACT16827 74ACT16827
Contextual Info: 54AC16827, 54ACT16827 74AC16827, 74ACT16827 20-BIT BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS _ TI0268— D 3544, JUNE 1990 Members of Texas Instruments Wldebus Family 54AC16827, 54ACT16827 . . . W D PACKAGE 74AC16S27, 74ACT16827 . . . DL PACKAGE

Contextual Info: 54ACT11353, 74ACT11353 DUAL 1-0F-4 DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS _SC AS045A- D3109, JUNE 1988 - REVISED APRIL 1993 * Inverting Versions of 54ACT11253 and 74ACT11253 54ACT11353 . . . J PACKAGE 74ACT11535 . . . D OR N PACKAGE

TI009

Contextual Info: 54AC11643, 74AC 11643 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS T I0095— D2957, JU LY 1987— REVISED MARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11643 . . . JT PACKAGE 74AC11643 . . . DW OR NT PACKAGE TOP VIEW Center-Pin V c c and GND Configurations to

nt802

Abstract: texas instrument Datatronics 48MHZ
Contextual Info: ^ j p DATATRONICS NT802-032 NT802-032 Token Ring Interface Module mam CjD O H T R T R Q N IC S NT802-032 Features • • • • Designed to meet IEEE 802.5 Specification Supports either 4Mbps or 16Mbps transmission over STP cable Industrial standard DIP package

Contextual Info: SN74LVC14 HEX SCHMITT-TRIGGER INVERTER MARCH 1993 D, DB, OR PW PACKAGE TOP VIEW 1A [ 1 EPIC (Enhanced-Performance Implanted CMOS) Submicron Process • Designed to Facilitate Incident Wave Switching for Line Impedances of 50 £2 or Greater • Typical V q l p (Output Ground Bounce)

Contextual Info: SN74LVC540 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS297 - JANUARY 1993 - RE V IS E D MARCH 1994 EPIC Enhanced-Performance Implanted CMOS Submicron Process DB, DW, OR PW PACKAGE (TOP VIEW) Typical V q u p (Output Ground Bounce) < 0.8 V at Vc c = 3 3 V, TA = 25°C

Contextual Info: CDC304 OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER SCAS325 - JULY 1990 - REVISED MARCH 1994 Replaces SN74AS304 Maximum Output Skew of 1 ns Maximum Pulse Skew of 1.5 ns TTL-Compatlble Inputs and Outputs D OR N PACKAGE TOP VIEW Q3 [ 1 Q 4[ 2 Center-Pin Vcc and GND Configurations

Contextual Info: 74AC11800 TRIPLE 4-INPUT AND/NAND GATES AUGUST 1992 - REVISED APRIL 1993 OW PACKAGE TOP VIEW Suitable for Use in Applications Such as: - Differential Line Drivers - Complementary Input Circuits for Decoders and Code Converters 1A[ 1y [ 1z [ 2Y[ gnd[ gnd[

Contextual Info: 74ACT11153 DUAL 1 OF 4 DATA SELECTOR/MULTIPLEXER _SCAS11BA - D3583, JUNE 1990-R E V IS E D APRIL 1993 * Inputs Are TTL-Voltage Compatible * Permits Multiplexing From N Lines to One Line D OR N PACKAGE {TOP VIEW f * Performs Parallel-to-Serial Conversion

SN74LVC10

Contextual Info: SN74LVC10 TRIPLE 3-INPUT POSITIVE-NAND GATE JA N U A R Y 1993 D, DB, OR PW PACKAGE TOP VIEW 1A [ EPIC (Enhanced-Performance Implanted CMOS) Submicron Process • Designed to Facilitate Incident Wave Switching for Line Impedances of 50 Q or Greater •

nt802

Abstract: 70MH
Contextual Info: f ï D DATATRONICS N T802-012 Token Ring Filter Module NT802-012 Features • • • • • Designed to meet IEEE 802.5 Specification Can be used in either transmit or receive channel over STP cable Supports either 4Mbps or 16Mbps transmission Industrial standard DIP package

Contextual Info: 54AC11032, 74AC11032 QUADRUPLE 2-INPUT POSITIVE-OR GATES TI0060— D2957, JULY 1987— REVISED MARCH 1990 54A C 11032 . . . J PACKAGE 74A C 11032 . . . D OR N PACKAGE • Flow-Through Architecture to Optimize PCB Layout TOP VIEW • Center-Pin V c c and GND Configurations to

431A4

Abstract: SCAS360
Contextual Info: SN74LVC16541 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS350 - MARCH 1994 * Member of the Texas Instruments Wldebus Family DQG OR DL PACKAGE CTOP VIEW • Typical V q l p Output Ground Bounce) < 0.8 V at VCc = 3.3 V, TA = 25°C • Typical V q h v (Output V q h Undershoot)