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    SN74LVC10 Search Results

    SN74LVC10 Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    SN74LVC10ADR Texas Instruments Triple 3-Input Positive-NAND Gate 14-SOIC -40 to 125 Visit Texas Instruments Buy
    SN74LVC10ADG4 Texas Instruments Triple 3-Input Positive-NAND Gate 14-SOIC -40 to 125 Visit Texas Instruments Buy
    SN74LVC10APW Texas Instruments Triple 3-Input Positive-NAND Gate 14-TSSOP -40 to 125 Visit Texas Instruments Buy
    SN74LVC10ARGYR Texas Instruments Triple 3-Input Positive-NAND Gate 14-VQFN -40 to 125 Visit Texas Instruments Buy
    SN74LVC10ANSR Texas Instruments Triple 3-Input Positive-NAND Gate 14-SO -40 to 125 Visit Texas Instruments
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    SN74LVC10 Price and Stock

    Rochester Electronics LLC SN74LVC10ARGYR

    IC GATE NAND 3CH 3-INP 14VQFN
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey SN74LVC10ARGYR Bulk 89,000 3,463
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    Rochester Electronics LLC SN74LVC10ADT

    IC GATE NAND 3CH 3-INP 14SOIC
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    DigiKey SN74LVC10ADT Bulk 61,750 681
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    Rochester Electronics LLC SN74LVC10APWT

    IC GATE NAND 3CH 3-INP 14TSSOP
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    DigiKey SN74LVC10APWT Bulk 60,500 681
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    Rochester Electronics LLC SN74LVC10ANSR

    IC GATE NAND 3CH 3-INP 14SO
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    DigiKey SN74LVC10ANSR Bulk 46,000 1,516
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    Rochester Electronics LLC SN74LVC10ADR

    IC GATE NAND 3CH 3-INP 14SOIC
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    DigiKey SN74LVC10ADR Bulk 42,132 2,664
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    Find more SN74LVC10 price and stock on Findchips.com

    SN74LVC10 Datasheets (116)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    SN74LVC10A Texas Instruments TRIPLE 3-INPUT POSITIVE-NAND GATE Original PDF
    SN74LVC10A Texas Instruments TRIPLE 3-INPUT POSITIVE-NAND GATE Original PDF
    SN74LVC10AD Texas Instruments SN74LVC10 - Triple 3-Input Positive-NAND Gate 14-SOIC -40 to 125 Original PDF
    SN74LVC10AD Texas Instruments Triple 3-Input Positive-NAND Gate Original PDF
    SN74LVC10AD Texas Instruments Triple 3-Input Positive-NAND Gate 14-SOIC -40 to 125 Original PDF
    SN74LVC10AD Texas Instruments TRIPLE 3-INPUT POSITIVE-NAND GATE Original PDF
    SN74LVC10AD Texas Instruments Logic - Gates and Inverters, Integrated Circuits (ICs), IC GATE NAND 3CH 3-INP 14-SOIC Original PDF
    SN74LVC10ADB Texas Instruments TRIPLE 3-INPUT POSITIVE-NAND GATE Original PDF
    SN74LVC10ADBLE Texas Instruments SN74LVC10 - Triple 3-Input Positive-NAND Gate 14-SSOP -40 to 125 Original PDF
    SN74LVC10ADBLE Texas Instruments TRIPLE 3-INPUT POSITIVE-NAND GATE Original PDF
    SN74LVC10ADBLE Texas Instruments Triple 3-Input Positive-NAND Gate 14-SSOP -40 to 125 Original PDF
    SN74LVC10ADBR Texas Instruments SN74LVC10 - Triple 3-Input Positive-NAND Gate 14-SSOP -40 to 125 Original PDF
    SN74LVC10ADBR Texas Instruments Triple 3-Input Positive-NAND Gate 14-SSOP -40 to 125 Original PDF
    SN74LVC10ADBR Texas Instruments Triple 3-Input Positive-NAND Gate Original PDF
    SN74LVC10ADBR Texas Instruments TRIPLE 3-INPUT POSITIVE-NAND GATE Original PDF
    SN74LVC10ADBR Texas Instruments Logic - Gates and Inverters, Integrated Circuits (ICs), IC GATE NAND 3CH 3-INP 14-SSOP Original PDF
    SN74LVC10ADBRE4 Texas Instruments SN74LVC10 - Triple 3-Input Positive-NAND Gate 14-SSOP -40 to 125 Original PDF
    SN74LVC10ADBRE4 Texas Instruments Triple 3-Input Positive-NAND Gate 14-SSOP -40 to 125 Original PDF
    SN74LVC10ADBRE4 Texas Instruments Triple 3-Input Positive-NAND Gate Original PDF
    SN74LVC10ADBRE4 Texas Instruments Logic - Gates and Inverters, Integrated Circuits (ICs), IC GATE NAND 3CH 3-INP 14-SSOP Original PDF

    SN74LVC10 Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    Untitled

    Abstract: No abstract text available
    Text: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE SCAS284K – JANUARY 1993 – REVISED SEPTEMBER 2002 D 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3C 3B 3A 3Y RGY PACKAGE TOP VIEW description/ordering information This triple 3-input positive-NAND gate is designed


    Original     		SN74LVC10A SCAS284K 000-V A114-A) A115-A) PDF

    Untitled

    Abstract: No abstract text available
    Text: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCAS284O – JANUARY 1993 – REVISED JULY 2005 FEATURES • 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3C 3B 3A 3Y RGY PACKAGE TOP VIEW 1B 2A 2B 2C 2Y VCC • 1 1 14 13 1C 12 1Y 2 3 4 11 3C 5 6 10 3B


    Original     		SN74LVC10A SCAS284O 000-V A114-A) A115-A) PDF

    Untitled

    Abstract: No abstract text available
    Text: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCAS284O – JANUARY 1993 – REVISED JULY 2005 FEATURES • 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3C 3B 3A 3Y RGY PACKAGE TOP VIEW 1B 2A 2B 2C 2Y VCC • 1 1 14 13 1C 12 1Y 2 3 4 11 3C 5 6 10 3B


    Original     		SN74LVC10A SCAS284O 000-V A114-A) A115-A) PDF

    Untitled

    Abstract: No abstract text available
    Text: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCAS284O – JANUARY 1993 – REVISED JULY 2005 FEATURES • 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3C 3B 3A 3Y RGY PACKAGE TOP VIEW 1B 2A 2B 2C 2Y VCC • 1 1 14 13 1C 12 1Y 2 3 4 11 3C 5 6 10 3B


    Original     		SN74LVC10A SCAS284O PDF

    SN74LVC10

    Abstract: No abstract text available
    Text: SN74LVC10 TRIPLE 3-INPUT POSITIVE-NAND GATE JA N U A R Y 1993 D, DB, OR PW PACKAGE TOP VIEW 1A [ EPIC (Enhanced-Performance Implanted CMOS) Submicron Process • Designed to Facilitate Incident Wave Switching for Line Impedances of 50 Q or Greater •


    OCR Scan     		SN74LVC10 65-mm MIL-STD-883C, PDF

    SN74LVC10A

    Abstract: No abstract text available
    Text: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE S C A S284D - JA N U A R Y 1993 - R EVISED JA N U A R Y 1997 EPIC Enhanced-Performance Implanted D, DB, O R PW PACKAGE (TOP VIEW CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V


    OCR Scan     		MIL-STD-883, JESD-17 SN74LVC10A SCAS284D SN74LVC10A PDF

    122B4

    Abstract: SN74LVC10A
    Text: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE SC A S 284F - JA N U A R Y 1993 - R EVISED JU NE 1998 • • • • • • • EPIC Enhanced-Performance Implanted D, DB, O R PW PACKAGE (TOP VIEW CMOS) Submicron Process ESD Protection Exceeds 2000 V Per


    OCR Scan     		SN74LVC10A SCAS284F MIL-STD-883, 10MHz, 122B4 SN74LVC10A PDF

    SN74LVC10A

    Abstract: No abstract text available
    Text: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE SCAS284G – JANUARY 1993 – REVISED OCTOBER 1998 D D D D D D D EPIC  Enhanced-Performance Implanted CMOS Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)


    Original     		SN74LVC10A SCAS284G MIL-STD-883, SN74LVC10A PDF

    Untitled

    Abstract: No abstract text available
    Text: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE SCAS284E - JANUARY 1993 - REVISED JANUARY 1998 • EPIC Enhanced-Performance Implanted CMOS Submicron Process • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)


    OCR Scan     		SN74LVC10A SCAS284E MIL-STD-883, JESD17 PDF

    Untitled

    Abstract: No abstract text available
    Text: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE SCAS284J – JANUARY 1993 – REVISED AUGUST 2002 D 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3C 3B 3A 3Y RGY PACKAGE TOP VIEW description/ordering information This triple 3-input positive-NAND gate is designed


    Original     		SN74LVC10A SCAS284J 000-V A114-A) A115-A) PDF

    Untitled

    Abstract: No abstract text available
    Text: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE SCAS284H – JANUARY 1993 – REVISED MARCH 2002 D D D D D D, DB, NS, OR PW PACKAGE TOP VIEW Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C


    Original     		SN74LVC10A SCAS284H 000-V A114-A) A115-A) PDF

    Untitled

    Abstract: No abstract text available
    Text: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCAS284O – JANUARY 1993 – REVISED JULY 2005 FEATURES • 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3C 3B 3A 3Y RGY PACKAGE TOP VIEW 1B 2A 2B 2C 2Y VCC • 1 1 14 13 1C 12 1Y 2 3 4 11 3C 5 6 10 3B


    Original     		SN74LVC10A SCAS284O 000-V A114-A) A115-A) PDF

    Untitled

    Abstract: No abstract text available
    Text: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE SCAS284I – JANUARY 1993 – REVISED JULY 2002 D D D D D D D D, DB, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 4.9 ns Typical VOLP (Output Ground Bounce)


    Original     		SN74LVC10A SCAS284I 000-V A114-A) A115-A) PDF

    Untitled

    Abstract: No abstract text available
    Text: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCAS284O – JANUARY 1993 – REVISED JULY 2005 FEATURES • 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3C 3B 3A 3Y RGY PACKAGE TOP VIEW 1B 2A 2B 2C 2Y VCC • 1 1 14 13 1C 12 1Y 2 3 4 11 3C 5 6 10 3B


    Original     		SN74LVC10A SCAS284O 000-V A114-A) A115-A) PDF

    Untitled

    Abstract: No abstract text available
    Text: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCAS284O – JANUARY 1993 – REVISED JULY 2005 FEATURES • 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3C 3B 3A 3Y RGY PACKAGE TOP VIEW 1B 2A 2B 2C 2Y VCC • 1 1 14 13 1C 12 1Y 2 3 4 11 3C 5 6 10 3B


    Original     		SN74LVC10A SCAS284O 000-V A114-A) A115-A) G3157 SNS74LVC2G53 scyb014 scyb005 scym001 PDF

    Untitled

    Abstract: No abstract text available
    Text: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCAS284O – JANUARY 1993 – REVISED JULY 2005 FEATURES • 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3C 3B 3A 3Y RGY PACKAGE TOP VIEW 1B 2A 2B 2C 2Y VCC • 1 1 14 13 1C 12 1Y 2 3 4 11 3C 5 6 10 3B


    Original     		SN74LVC10A SCAS284O 000-V A114-A) A115-A) PDF

    A115-A

    Abstract: SN74LVC10A SN74LVC10AD SN74LVC10ADR SN74LVC10ARGYR
    Text: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCAS284O – JANUARY 1993 – REVISED JULY 2005 FEATURES • 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3C 3B 3A 3Y RGY PACKAGE TOP VIEW 1B 2A 2B 2C 2Y VCC • 1 1 14 13 1C 12 1Y 2 3 4 11 3C 5 6 10 3B


    Original     		SN74LVC10A SCAS284O A115-A SN74LVC10A SN74LVC10AD SN74LVC10ADR SN74LVC10ARGYR PDF

    Untitled

    Abstract: No abstract text available
    Text: SN74LVC10 TRIPLE 3-INPUT POSITIVE-NAND GATE SCAS284 - JANUARY 1993 - REVISED MARCH 1994 EPIC Enhanced-Performance Implanted CMOS Submicron Process D, DB, OR PW PACKAGE (TOP VIEW) Typical V q l p (Output Ground Bounce) < 0.8 V at Vc c = 3.3 V, TA = 25°C


    OCR Scan     		SN74LVC10 SCAS284 PDF

    A115-A

    Abstract: SN74LVC10A SN74LVC10AD SN74LVC10ADR SN74LVC10ARGYR
    Text: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCAS284O – JANUARY 1993 – REVISED JULY 2005 FEATURES • 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3C 3B 3A 3Y RGY PACKAGE TOP VIEW 1B 2A 2B 2C 2Y VCC • 1 1 14 13 1C 12 1Y 2 3 4 11 3C 5 6 10 3B


    Original     		SN74LVC10A SCAS284O A115-A SN74LVC10A SN74LVC10AD SN74LVC10ADR SN74LVC10ARGYR PDF

    Untitled

    Abstract: No abstract text available
    Text: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE SCAS284K – JANUARY 1993 – REVISED SEPTEMBER 2002 D 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3C 3B 3A 3Y RGY PACKAGE TOP VIEW description/ordering information This triple 3-input positive-NAND gate is designed


    Original     		SN74LVC10A SCAS284K 000-V A114-A) A115-A) SN74LVC10ARGYR SN74LVC10A SCEM011A, PDF

    SN74LVC10A

    Abstract: No abstract text available
    Text: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE S C AS 284E - JA N U A R Y 1993 - R EVISED JA N U A R Y 1998 EPIC Enhanced-Performance Implanted D, DB, O R PW PACKAGE (TOP VIEW CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V


    OCR Scan     		MIL-STD-883, SN74LVC10A SCAS284E SN74LVC10A PDF

    A115-A

    Abstract: SN74LVC10A SN74LVC10AD SN74LVC10ADR SN74LVC10ARGYR
    Text: SN74LVC10A TRIPLE 3ĆINPUT POSITIVEĆNAND GATE SCAS284M − JANUARY 1993 − REVISED JULY 2003 D 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3C 3B 3A 3Y RGY PACKAGE TOP VIEW description/ordering information This triple 3-input positive-NAND gate is designed


    Original     		SN74LVC10A SCAS284M SN74LVC10A A115-A SN74LVC10AD SN74LVC10ADR SN74LVC10ARGYR PDF

    Untitled

    Abstract: No abstract text available
    Text: SN74LVC10 TRIPLE 3-INPUT POSITIVE-NAND GATE S C A S 2 8 4 -JANUARY 1 9 9 3 -R E V IS E D MARCH 1994 D, DB, OR PW PACKAGE TOP VIEW EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Typical V q l p (Output Ground Bounce) < 0.8 V at Vc c = 3.3 V, TA = 25°C


    OCR Scan     		SN74LVC10 SCAS284-JANUARY 1993-REVISED SN74LVC10 -100mA 010044M PDF

    LC10A

    Abstract: No abstract text available
    Text: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCAS284O – JANUARY 1993 – REVISED JULY 2005 FEATURES • 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3C 3B 3A 3Y RGY PACKAGE TOP VIEW 1B 2A 2B 2C 2Y VCC • 1 1 14 13 1C 12 1Y 2 3 4 11 3C 5 6 10 3B


    Original     		SN74LVC10A SCAS284O 000-V A114-A) A115-A) LC10A PDF