TBPC Search Results

M44C260

Abstract: M48C260 0014D1 EPI EEPROM CPU AGB A
Contextual Info: Tem ic M48C260 TELEFUNKEN Semiconductors MARC4 - 4-bit Microcontroller The M48C260 is a member of the TEMIC family of 4-bit single chip microcontrollers. It is the user programmable version of the M44C260. It contains EEPROM program memory, RAM, EEPROM data memory, parallel I/O ports,

AA 170 circit diagram

Abstract: 256KX16 MSM5416256 ucas zip
Contextual Info: Technical Information OKI Semiconductor MSM5416256/MSM54V16256 ¿ Lo w voltage version or V-voreion _ 262,144 Words x 16 Bits GRAPHICS BURST A C C ESS MEMORY

Contextual Info: Lattice ispLSI and pLSI 1048E ; Semiconductor I Corporation High-Density Programmable Logic Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC O u tpu t R outing Pool — 8,000 PLD Gates | | O u tpu t R outing Pool ü m u lü lü llS i!

82599EN

Contextual Info: Intel 82599 10 GbE Controller Datasheet Networking Division ND PRODUCT FEATURES General                                  Dual port 10 GbE device or Single Port device (82599EN)

Contextual Info: HM5118160BI Series 1048576-word x 16-bit Dynamic Random Access Memory HITACHI ADE-203-580A Z Rev. 1.0 May. 20, 1996 Description T he H itachi H M 5118160B I is a C M O S dynam ic R A M organized as 1,048,576-w ord x 16-bit. It em ploys the m ost advanced C M O S technology fo r high perform ance and low pow er. T he H M 5118160B I offers

Contextual Info: HM51W17800 Series 2,097,152-word x 8-bit Dynamic RAM HITACHI ADE-203-664C Z Rev. 3.0 Feb. 24,1997 Description The Hitachi HM51W17800 is a CMOS dynamic RAM organized 2,097,152-word x 8-bit. It employs the most advanced CMOS technology for high performance and low power. The HM51W17800 offers Fast

dell 9400

Abstract: 10GBASE-T cable pairs pinout dell motherboard schematic nec 2501 schematic diagram offline UPS Dell 40 pin I/0 pinout honeywell TS2 water filling station circuit diagram pentium 4 honeywell pcm45
Contextual Info: Intel 82598 10 GbE Ethernet Controller Open Source Datasheet PRODUCT FEATURES General „ Serial Flash Interface „ 4-wire SPI EEPROM Interface „ Configurable LED operation for software or OEM customization of LED displays „ Protected EEPROM space for private configuration

RG703

Abstract: ch8c ch6b Motorola LSC microcontroller DS26528 DS26521 DS26522 DS26524 DS26524GN 1103h
Contextual Info: DS26524 Quad T1/E1/J1 Transceiver www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS26524 is a single-chip 4-port framer and line interface unit LIU combination for T1, E1, and J1 applications. Each channel is independently configurable, supporting both long-haul and short-haul

20EF TRANSFORMER

Abstract: TRANSFORMER 20EF 20F9 rexton AAIS mark csc 9102 D3318
Contextual Info: PRODUCT PREVIEW GENERAL DESCRIPTION The DS26519 is a single-chip 16-port framer and line interface unit LIU combination for T1, E1, and J1 applications. Each port is independently configurable, supporting both long-haul and short-haul lines. The DS26518 is a 8-port SCT. The DS26514 is a 4-port

11290

Abstract: TLS14
Contextual Info: DS26528 Octal T1/E1/J1 Transceiver www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS26528 is a single-chip 8-port framer and line interface unit LIU combination for T1, E1, and J1 applications. Each channel is independently configurable, supporting both long-haul and short-haul

MC141512

Abstract: MC141515T motorola v3 lcd display 0170 v1 jx 5020 MC141512T1 MC141515 MCC141512 can 82250
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC141512 MC141515 LCD Backplane Drivers CMOS The MC141512 and MC141515 are high voltage passive LCD backplane driver chips. The MC141512 provides 80 high voltage LCD driving signals whereas the MC141515 provides 160 high voltage LCD driving signals.

AT25F2048

Abstract: 25F2048 X101 X110 2455H
Contextual Info: Features • • • • • • • • • • • • • • • Serial Peripheral Interface SPI Compatible Supports SPI Modes 0 (0,0) and 3 (1,1) 33 MHz Clock Rate Byte Mode and 256-byte Page Mode for Program Operations Sector Architecture: – Four Sectors with 64K Bytes Each

AT25FS010

Abstract: X101 X110
Contextual Info: Features • Serial Peripheral Interface SPI Compatible • Supports SPI Modes 0 (0,0) and 3 (1,1) – Datasheet describes Mode 0 Operation • 50 MHz Clock Rate • Byte Mode and Page Mode Program (1 to 256 Bytes) Operations • Sector/Block/Page Architecture

ch7d

Contextual Info: DS26528 Octal T1/E1/J1 Transceiver www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS26528 is a single-chip 8-port framer and line interface unit LIU combination for T1, E1, and J1 applications. Each channel is independently configurable, supporting both long-haul and short-haul

256kx16 ucas zip

Contextual Info: Technical Information OKI Semiconductor MSM5416256/MSM54V16256 {Standard-version _ Lowvoltago vflrsionor V-voremn)_ 262,144 Words x 16 Bits GRAPHICS BURST ACCESS MEMORY GENERAL DESCRIPTION The MSM5416256 is a high speed 256KX16 configuration burst access memory for high performance

AT25F1024A

Abstract: X101 X110
Contextual Info: Features • Serial Peripheral Interface SPI Compatible • Supports SPI Modes 0 (0,0) and 3 (1,1) – Datasheet Describes Mode 0 Operation • 33 MHz Clock Rate • Byte Mode and 256-byte Page Mode for Program Operations • Sector Architecture: • •

BRA 94

Abstract: BP01 M44C260 M48C260 ccs 9014 Temic date array bra94
Contextual Info: M44C260/M48C260 MARC4 – 4-bit Microcontroller The M44C260 and M48C260 are members of the TEMIC family of 4-bit single chip microcontrollers. The M48C260 is the user programmable version of the M44C260. It contains an EEPROM program memory instead of a ROM. Both

a3568

Abstract: S-80141ALMC aplication notes w25q32b quanta 6320 XL710 26 Pin GPIO Connector Header Extender 90 Degree Angle TXAL 228 B
Contextual Info: Intel Ethernet Controller XL710 Datasheet Networking Division ND Revision: 2.1 December 2014 Legal Lines and Disclaimers No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a

Contextual Info: DS26519 16-Port T1/E1/J1 Transceiver www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS26519 is a single-chip 16-port framer and line interface unit LIU combination for T1, E1, and J1 applications. Each port is independently configurable, supporting both long-haul and short-haul lines. The

Contextual Info: Lattice* is p L S I “ ; S e m ico nd u cto r • ■ ■ C orporation a n d p L S I 2 1 2 8 High Density Programmable Logic Functional Block Diagram Features • HIGH DENSITY PROGRAMMABLE LOGIC — — — — — 6000 PLD Gates 128 I/O Pins, Eight Dedicated Inputs

wavelet transform FPGA

Abstract: documentation for 32 bit alu in vlsi JPEG2000 JPEG2000-Part JPEG200
Contextual Info: Nios II Embedded Processor Design Contest—Outstanding Designs 2005 Second Prize Nios II Processor-Based Hardware/Software Co-Design of the JPEG2000 Standard Institution: University of New South Wales Participants: Mike Dyer, Amit Kumar Gupta, and Natalie Galin

AEL2005

Abstract: FLX07 NetLogic Microsystems AEL2005 2N1150 10G KR PHy pxe teaming wol network search engine netlogic Delta Electronics dps 800 3192* intel "network interface cards"
Contextual Info: Intel 82598 10 GbE Controller Datasheet LAN Access Division FEATURES General  Serial Flash Interface  4-wire SPI EEPROM Interface  Configurable LED operation for software or OEM customization of LED displays  Protected EEPROM space for private configuration

dallas semiconductor IC DS 1242

Abstract: 063a st rcc23 RG703 BUS34 bel 1515 hybrid ic Motorola LSC microcontroller mps 0514 MPS 0713 P/LM 1709 cb
Contextual Info: DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS26556 is a quad, software-selectable T1, E1, or J1 transceiver with a cell/packet/TDM interface. It is composed of four framer/formatters + LIUs, and a UTOPIA cell , POS-PHY

Contextual Info: Features • • • • • • • • • • • • • • Serial Peripheral Interface SPI Compatible Supports SPI Modes 0 (0,0) and 3 (1,1) 20 MHz Clock Rate Byte Mode and 256-byte Page Mode for Program Operations Sector Architecture: – Two Sectors with 32K Bytes Each (512K)