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    Maxim Integrated Products MAX11048ETN-

    IC ADC 16BIT SAR 56TQFN
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    DigiKey MAX11048ETN- Tube 37 1
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    Texas Instruments DSLVDS1047-1048EVM

    DEVELOPMENT POWER MANAGEMENT
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    DigiKey DSLVDS1047-1048EVM Box 12 1
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    Mouser Electronics DSLVDS1047-1048EVM 24
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    Texas Instruments TLV61048EVM-042

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    DigiKey TLV61048EVM-042 Box 1 1
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    Mouser Electronics TLV61048EVM-042 1
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    Maxim Integrated Products MAX11048ECB-

    IC ADC 16BIT PAR 250KSPS 64TQFP
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    DigiKey MAX11048ECB- Tray 160
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    MAX11048ECB- Tray 160
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    Rochester Electronics LLC ISPLSI1048E-90LT

    IC CPLD 192MC 10NS 128TQFP
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    DigiKey ISPLSI1048E-90LT Bulk 7
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    1048E Datasheets (2)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    1048E Lattice Semiconductor High-Density Programmable Logic Original PDF
    1048EA Lattice Semiconductor In-System Programmable High Density PLD Original PDF

    1048E Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    1048E

    Abstract: 1048C 0124-48C 1048E-125
    Text: ispLSI 1048E High-Density Programmable Logic Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 8,000 PLD Gates — 96 I/O Pins, Twelve Dedicated Inputs — 288 Registers — High-Speed Global Interconnects — Wide Input Gating for Fast Counters, State


    Original     		PDF 1048E 1048C 125QFP 128-Pin 1048E-90LQ* 1048E-90LT* 1048E-70LQ 1048E-70LT 1048E 1048C 0124-48C 1048E-125

    1048e

    Abstract: 1048C
    Text: ispLSI 1048E In-System Programmable High Density PLD Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 8,000 PLD Gates — 96 I/O Pins, Twelve Dedicated Inputs — 288 Registers — High-Speed Global Interconnects — Wide Input Gating for Fast Counters, State


    Original     		PDF 1048E 1048C 1048E-100LQ 1048E-100LT 128-Pin 1048E-90LQ* 1048E-90LT* 1048e 1048C

    1048C

    Abstract: 1048E
    Text: ispLSI 1048E High-Density Programmable Logic Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 8,000 PLD Gates — 96 I/O Pins, Twelve Dedicated Inputs — 288 Registers — High-Speed Global Interconnects — Wide Input Gating for Fast Counters, State


    Original     		PDF 1048E 1048C 128-Pin 1048E-90LQ* 1048E-90LT* 1048E-70LQ 1048E-70LT 1048E-50LQ* 1048C 1048E

    1048E

    Abstract: ispLSI 1048E-70LT 1048C 1048E-100LQN
    Text: LeadFree Package Options Available! ispLSI 1048E In-System Programmable High Density PLD Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 8,000 PLD Gates — 96 I/O Pins, Twelve Dedicated Inputs Output Routing Pool Output Routing Pool F7 F6 F5 F4 F3 F2 F1 F0


    Original     		PDF 1048E 1048C 1048E-125LTN 1048E-100LQN 1048E-100LTN 128-Pin 1048E ispLSI 1048E-70LT 1048C 1048E-100LQN

    100LQ128

    Abstract: 1048C 1048E 1048EA
    Text: ispLSI 1048EA In-System Programmable High Density PLD Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 8,000 PLD Gates — 96 I/O Pins, Eight Dedicated Inputs — 288 Registers — High-Speed Global Interconnects — Wide Input Gating for Fast Counters, State


    Original     		PDF 1048EA 1048C 1048E 128-Pin 0212/1048EA 1048EA 1048EA-170LQ128 1048EA-170LT128 100LQ128 1048E

    "XOR Gate"

    Abstract: 1024EA 1016e 1016EA 1032EA 1048EA
    Text: ispLSI 1000EA Family Architectural Description October 2001 Introduction The ispLSI 1000EA Family of High Density Programmable Logic devices includes the 1016EA, 1024EA, 1032EA and 1048EA devices. Each family member offers internal registers, input registers, Universal I/O pins, dedicated


    Original     		PDF 1000EA 1016EA, 1024EA, 1032EA 1048EA t20ptxor) 1032EA-200 "XOR Gate" 1024EA 1016e 1016EA 1032EA

    1048e

    Abstract: 1048C
    Text: ispLSI 1048E In-System Programmable High Density PLD Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 8,000 PLD Gates — 96 I/O Pins, Twelve Dedicated Inputs — 288 Registers — High-Speed Global Interconnects — Wide Input Gating for Fast Counters, State


    Original     		PDF 1048E 1048C 1048E-90LQ 1048E-90LT 1048E-70LQ 1048E-70LT 1048E-50LQ 128-Pin 1048e 1048C

    1048E

    Abstract: 1048E-50 0127A 1048C
    Text: ispLSI 1048E In-System Programmable High Density PLD Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 8,000 PLD Gates — 96 I/O Pins, Twelve Dedicated Inputs — 288 Registers — High-Speed Global Interconnects — Wide Input Gating for Fast Counters, State


    Original     		PDF 1048E 1048C 1048E-100LQ 1048E-100LT 128-Pin 1048E-90LQ* 1048E-90LT* 1048E 1048E-50 0127A 1048C

    1048C

    Abstract: 1048E 1048EA isplsi1048c 1048EA100LT128
    Text: ispLSI 1048EA In-System Programmable High Density PLD Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 8,000 PLD Gates — 96 I/O Pins, Eight Dedicated Inputs — 288 Registers — High-Speed Global Interconnects — Wide Input Gating for Fast Counters, State


    Original     		PDF 1048EA 1048C 1048E 128-Pin 0212/1048EA 1048EA 1048EA-170LQ128 1048EA-170LT128 1048E isplsi1048c 1048EA100LT128

    R1C390

    Abstract: 1048e 100lq128 1048C 1048E 1048EA
    Text: ispLSI 1048EA In-System Programmable High Density PLD Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 8,000 PLD Gates — 96 I/O Pins, Eight Dedicated Inputs — 288 Registers — High-Speed Global Interconnects — Wide Input Gating for Fast Counters, State


    Original     		PDF 1048EA 1048C 1048E IE28-Pin 1048EA 0212/1048EA 1048EA-170LQ128 1048EA-170LT128 128-Pin R1C390 1048e 100lq128 1048E

    1048E

    Abstract: 1048E-50 NS-344
    Text: ® ispLSI and pLSI 1048E High-Density Programmable Logic • ispLSI and pLSI DEVELOPMENT TOOLS pDS® Software — Easy to Use PC Windows Interface — Boolean Logic Compiler — Manual Partitioning — Automatic Place and Route — Static Timing Table


    Original     		PDF 1048E 1048E 1048E-50 NS-344

    1048E

    Abstract: ispLSI 1048E90LQ 1048E-50 1048E70LQ
    Text: ispLSI and pLSI 1048E ® High-Density Programmable Logic Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 8,000 PLD Gates — 96 I/O Pins, Twelve Dedicated Inputs — 288 Registers — High-Speed Global Interconnects — Wide Input Gating for Fast Counters, State


    Original     		PDF 1048E 1048E ispLSI 1048E90LQ 1048E-50 1048E70LQ

    Untitled

    Abstract: No abstract text available
    Text: ispLSI 1048EA In-System Programmable High Density PLD Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 8,000 PLD Gates — 96 I/O Pins, Eight Dedicated Inputs — 288 Registers — High-Speed Global Interconnects — Wide Input Gating for Fast Counters, State


    Original     		PDF 1048EA 1048C 1048E 128-Pin 0212/1048EA 1048EA 1048EA-170LQ128 1048EA-170LT128

    1048C

    Abstract: 1048E 1048EA
    Text: ispLSI 1048EA In-System Programmable High Density PLD Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 8,000 PLD Gates — 96 I/O Pins, Eight Dedicated Inputs — 288 Registers — High-Speed Global Interconnects — Wide Input Gating for Fast Counters, State


    Original     		PDF 1048EA 1048C 1048E 128-Pin 0212/1048EA 1048EA 1048EA-170LQ128 1048EA-170LT128 1048E

    2032LV

    Abstract: teradyne z1800 tester manual teradyne z8000 tester manual 1016E 1032E 1048C 3256E pDS4102-J44 Quasar gr228x
    Text: ISP Daisy Chain Download Reference Manual Version 5.0 Technical Support Line: 1-800-LATTICE or 408 428-6414 pDS4104 -RM Rev 5.0 Copyright This document may not, in whole or part, be copied, photocopied, reproduced, translated, or reduced to any electronic medium or machine-readable form without


    Original     		PDF 1-800-LATTICE pDS4104 2032LV teradyne z1800 tester manual teradyne z8000 tester manual 1016E 1032E 1048C 3256E pDS4102-J44 Quasar gr228x

    Untitled

    Abstract: No abstract text available
    Text: Lattice ispLSI and pLSI 1048E ; Semiconductor I Corporation High-Density Programmable Logic Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC O u tpu t R outing Pool — 8,000 PLD Gates | | O u tpu t R outing Pool ü m u lü lü llS i!


    OCR Scan     		PDF 1048E 1048E 1048E-90LQ 128-Pin 1048E-70LQ 1048E-50LQ

    Untitled

    Abstract: No abstract text available
    Text: Lattice ispLSr and pLS r 1048E ; ” Semiconductor • ■ ■ Corporation High-Density Programmable Logic Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 8,000 PLD Gates — 96 I/O Pins, Twelve Dedicated Inputs — 288 Registers


    OCR Scan     		PDF 1048E 1048E 1048E-90LQ 128-Pin 1048E-90LT 1048E-70LQ 1048E-70LT

    Untitled

    Abstract: No abstract text available
    Text: Lattica ispLSI and pLSI 1048E ;Semiconductor I Corporation High-Density Programmable Logic Functional Block Diagram Features • HIGH DENSITY PROGRAMMABLE LOGIC — 8,000 PLD Gates — 96 I/O Pins, Twelve Dedicated Inputs — 288 Registers — High-Speed Global Interconnects


    OCR Scan     		PDF 1048E 128-Pin 1048E -90LT -70LQ -70LT

    Untitled

    Abstract: No abstract text available
    Text: Lattice is p L S r and p L S r 1048E ;Semiconductor ICorporation High-Density Programmable Logic Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 8,000 PLD Gates — 96 I/O Pins, Twelve Dedicated Inputs — 288 Registers — High-Speed Global Interconnects


    OCR Scan     		PDF 1048E

    Untitled

    Abstract: No abstract text available
    Text: Lattica ispLSI 1048E I Semiconductor I Corporation High-Density Programmable Logic Functional Block Diagram Features • HIGH DENSITY PROGRAMMABLE LOGIC — 8,000 PLD Gates — 96 I/O Pins, Twelve Dedicated Inputs — 288 Registers — High-Speed Global Interconnects


    OCR Scan     		PDF 1048E 1048C 128-P 1048E -70LQ

    Untitled

    Abstract: No abstract text available
    Text: Lattice ispLSI and pLSI 1048E ! Semiconductor •Corporation High-Density Programmable Logic Functional Block Diagram Features • HIGH DENSITY PROGRAMMABLE LOGIC — 8,000 PLD Gates — 96 I/O Pins, Twelve Dedicated Inputs — 288 Registers — High-Speed Global Interconnects


    OCR Scan     		PDF 1048E 1048E 128-P

    LSI1048E

    Abstract: No abstract text available
    Text: Lattice' ispLSI9 1048E ;Semiconductor I Corporation In-System Programmable High Density PLD F e a tu re s F u n c tio n a l B lo c k D iagram • HIGH DENSITY PROGRAMMABLE LOGIC — 8,000 PLD Gates — 96 I/O Pins, Twelve Dedicated Inputs — 288 Registers


    OCR Scan     		PDF 1048C 1048E-125LQ 1048E-125LT 1048E-100LQ 1048E-100LT 1048E-90LQ* 1048E-90LT* 1048E-70LQ 1048E-70LT 1048E-50LQ" LSI1048E

    Untitled

    Abstract: No abstract text available
    Text: Lattice ispLSI9 1048E ;Semiconductor I Corporation High-Density Programmable Logic Functional Block Diagram Features • HIGH DENSITY PROGRAMMABLE LOGIC — 8,000 PLD Gates — 96 I/O Pins, Twelve Dedicated Inputs — 288 Registers — High-Speed Global Interconnects


    OCR Scan     		PDF 1048C 1048E-125LQ 1048E-125LT 1048E-100LQ 1048E-100LT 128-Pin

    ispLS11048

    Abstract: kOOO5
    Text: Lattica ispLSI 1048E I Semiconductor I Corporation High-Density Programmable Logic Functional Block Diagram Features • HIGH DENSITY PROGRAMMABLE LOGIC — 8,000 PLD Gates — 96 I/O Pins, Twelve Dedicated Inputs — 288 Registers — High-Speed Global Interconnects


    OCR Scan     		PDF 1048E 1048C 133-Pin ispLS11048 kOOO5