TBD 234 V8 Search Results

MT18JSF51272PKZ-1G4K1

Contextual Info: 4GB x72, ECC, DR 244-Pin DDR3 SDRAM Mini-RDIMM Features DDR3 SDRAM Mini-RDIMM MT18JSF51272PKZ – 4GB Features Figure 1: 244-Pin Mini-RDIMM (MO-244 R/C C) • DDR3 functionality and operations supported as defined in the component data sheet • 244-pin, registered dual in-line, 82mm, memory

624 CCGA

Abstract: RTAX2000 TBD 234 V12 CQFP verilog hdl code for triple modular redundancy
Contextual Info: Advanced v0.4 RTAX-S Family FPGAs Special Features for Space • • • • • • • • • • • Up to 10,752 SEU Hardened Flip-Flops Eliminate Software TMR Necessity >LET th 37 LET, GEO SEU Rate <10-10 Errors/Bit-Day Expected SRAM Upset Rate of <10-10 Errors/Bit-Day

UT699RH

Abstract: SpaceWire Dose
Contextual Info: RadHard Standard Products UT699RH RadHard 32-bit Fault-Tolerant LEON 3FT/SPARCTM V8 Processor Advanced Data Sheet January 29, 2008 INTRODUCTION The UT699RH is a RadHard pipelined monolithic, highperformance, fault-tolerant SPARCTM V8 Processor. It has been

BC 247

Abstract: bc 149 c X1401 HP3070 PM7364 BC 251
Contextual Info: - PMC Sierra PM7364 FREEDM - 32 BSDL description - Written by: James Lamond - Verified electrically against PM7364 FREEDM-32 - Using HP3070 Boundary Scan S/W revision B.02.54 - PM7364 BSDL Revison: 04 - Hewlett Packard Canada Ltd - Revised for Rev D device by Richard Steedman, PMC

G4 BC 30

Abstract: BC 247 TBD 234 V12 M9809 HP3070 PM5342 PM7366 X1631 X1-73 bc 205
Contextual Info: BSDL SOURCE CODE - PMC_Sierra_Cells for PMC - Sierra revision : VHDL Package and Package Body 1.0 created by : James Lamond Hewlett Packard Canada Ltd date : 20 December 1995 package PMC_Sierra_Cells is use STD_1149_1_1990.all; constant cele0 : CELL_INFO;

asr19

Contextual Info: RadHard Standard Products UT699RH RadHard 32-bit Fault-Tolerant LEON 3FT/SPARCTM V8 Processor Advanced Data Sheet January 15, 2008 INTRODUCTION The UT699RH is a RadHard pipelined monolithic, highperformance, fault-tolerant SPARCTM V8 Processor. It has been

RTAX2000

Abstract: footprint cqfp 280 RTAX1000S actel cqfp 84
Contextual Info: A dv an c ed v0 .5 RTAX-S RadTolerant FPGAs Designed for Space • • • • • • • • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETth > 60 MeV-cm2/mg – SEU Rate < 10-10 Errors/Bit-Day in Worst-Case

4x1K

Abstract: edac 96 pin edac connector footprint cqfp 132 833 T12
Contextual Info: Advanced v0.5 RTAX-S RadTolerant FPGAs Designed for Space • • • • • • • • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETth > 60 MeV-cm2/mg – SEU Rate < 10-10 Errors/Bit-Day in Worst-Case

Contextual Info: A dv an c ed v0 .5 RTAX-S RadTolerant FPGAs Designed for Space • • • • • • • • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETth > 60 MeV-cm2/mg – SEU Rate < 10-10 Errors/Bit-Day in Worst-Case

uPD703128GJ

Abstract: uPD703128 uPD703129 uPD703129GJ TIC15 ON5278 transistor dd52 HC49US NDK America upD70312
Contextual Info: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT µPD703128, µPD703129 V850E/CA2TM JUPITER 32-/16-BIT ROMLESS MICROCONTROLLER DESCRIPTION The V850E/CA2 Jupiter ROM-less microcontroller is a member of NEC's V850 32-bit RISC family, which match the performance gains attainable with RISC-based controllers to the needs of embedded control

smd 3Ft 82

Abstract: smd 3ft thermal specifications UT699 UT699
Contextual Info: Standard Products UT699 32-bit Fault-Tolerant SPARCTM V8/LEON 3FT Processor Preliminary Data Sheet November 3, 2008 INTRODUCTION The UT699 is a pipelined monolithic, high-performance, faulttolerant SPARCTM V8/LEON 3FT Processor. The UT699 provides a 32-bit master/target PCI interface, including a 16 bit

5962-08228

Contextual Info: Standard Products UT699 32-bit Fault-Tolerant SPARCTM V8/LEON 3FT Processor Preliminary Data Sheet January 7, 2009 INTRODUCTION The UT699 is a pipelined monolithic, high-performance, faulttolerant SPARCTM V8/LEON 3FT Processor. The UT699 provides a 32-bit master/target PCI interface, including a 16 bit

Contextual Info: 1GB, 2GB, 4GB x72, ECC, SR 240-Pin DDR3 RDIMM Features DDR3 SDRAM RDIMM MT9JSF12872PZ – 1GB MT9JSF25672PZ – 2GB MT9JSF51272PZ – 4GB Features Figure 1: 240-Pin RDIMM (MO-269 R/C A – PCB 0692) • DDR3 functionality and operations supported as defined in the component data sheet

w32 smd transistor

Abstract: rtax250sl RTAX2000S w32 smd transistor 143 41-bit Carry Look-ahead Adder RTAX2000SL RTAX4000S BY415 RTAX4000D LG1152
Contextual Info: Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Radiation Performance Specifications • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeVcm2/mg – SEU Rate < 10-10 Errors/Bit-Day (worst case GEO)

624 CCGA

Abstract: CQ352 transistor prc 606 j rtax250 RTAX2000 rtax4000
Contextual Info: Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Radiation Performance Specifications • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeVcm2/mg – SEU Rate < 10-10 Errors/Bit-Day (worst case GEO)

Contextual Info: PRELIMINARY DATA SHEET 4GB DDR3 SDRAM SO-DIMM EBJ41UF8BAS0 512M words x 64 bits, 2 Ranks Specifications Features • Density: 4GB • Organization  512M words × 64 bits, 2 ranks • Mounting 16 pieces of 2G bits DDR3 SDRAM sealed in FBGA • Package: 204-pin socket type small outline dual in

EBJ41UF8BAS0

Abstract: DDR3 pcb layout raw card f so-dimm EBJ41UF8 E1545E20 EDJ2108 EDJ2104 EDJ2108BASE-DJ-F A2198 EDJ2108BASE-GN-F E1545
Contextual Info: PRELIMINARY DATA SHEET 4GB DDR3 SDRAM SO-DIMM EBJ41UF8BAS0 512M words x 64 bits, 2 Ranks Specifications Features • Density: 4GB • Organization  512M words × 64 bits, 2 ranks • Mounting 16 pieces of 2G bits DDR3 SDRAM sealed in FBGA • Package: 204-pin socket type small outline dual in

Contextual Info: PRELIMINARY DATA SHEET 2GB Unbuffered DDR3 SDRAM DIMM EBJ21EE8BAFA 256M words x 72 bits, 2 Ranks Specifications Features • Density: 2GB • Organization ⎯ 256M words × 72 bits, 2 ranks • Mounting 18 pieces of 1G bits DDR3 SDRAM sealed in FBGA • Package: 240-pin socket type dual in line memory

Contextual Info: Revision 1 SmartFusion2 System-on-Chip FPGAs Microsemi’s SmartFusion 2 SoC FPGAs integrate fourth generation flash-based FPGA fabric, an ARM® Cortex -M3 processor, and high performance communications interfaces on a single chip. The SmartFusion2 family is the industry’s lowest power, most

d 998

Abstract: LFX1200B-02F900I
Contextual Info: ispXPGA Family TM July 2002 Advance Data Sheet • Eight sysCLOCK Phase Locked Loops PLLs for Clock Management Features ■ Non-volatile, Infinitely Reconfigurable • • • • • • Instant-on - Powers up in microseconds via on-chip E2CMOS based memory

E1235E40

Abstract: EBJ21EE8BAFA
Contextual Info: DATA SHEET 2GB Unbuffered DDR3 SDRAM DIMM EBJ21EE8BAFA 256M words x 72 bits, 2 Ranks Specifications Features • Density: 2GB • Organization  256M words × 72 bits, 2 ranks • Mounting 18 pieces of 1G bits DDR3 SDRAM sealed in FBGA • Package: 240-pin socket type dual in line memory

E1248

Contextual Info: PRELIMINARY DATA SHEET 2GB Unbuffered DDR3 SDRAM DIMM EBJ21EE8BAWA 256M words x 72 bits, 2 Ranks Specifications Features • Density: 2GB • Organization  256M words × 72 bits, 2 ranks • Mounting 18 pieces of 1G bits DDR3 SDRAM sealed in FBGA • Package: 240-pin socket type dual in line memory

Pressure Sensor Spx 3058

Abstract: V850E2M 32-bit Microcontroller Core Architecture
Contextual Info: User’s Manual V850E2/Sx4-H 32 Hardware User’s Manual RENESAS MCUs V850E2/Sx4-H microcontrollers [Preliminary] All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by

edj1116

Abstract: EDJ1108 E1248E DDR3-800
Contextual Info: DATA SHEET 2GB Unbuffered DDR3 SDRAM DIMM EBJ21EE8BAWA 256M words x 72 bits, 2 Ranks Specifications Features • Density: 2GB • Organization  256M words × 72 bits, 2 ranks • Mounting 18 pieces of 1G bits DDR3 SDRAM sealed in FBGA • Package: 240-pin socket type dual in line memory