4X1K Search Results

LGA 478 SOCKET PIN LAYOUT

Abstract: RTAX2000
Contextual Info: v5.2 RTAX-S/SL RadTolerant FPGAs Radiation Performance Leading-Edge Performance • • • • • • • • • • SEU-Hardened Registers Eliminate the Need for TripleModule Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg

Contextual Info: Advanced v0.3  RTAX-S Family FPGAs Sp e ci a l F ea t ur es f o r Sp a ce • Up to 10,752 SEU Hardened Flip-Flops Eliminate Software TMR Necessity >LET th 37 LET, GEO SEU Rate <10-10 Errors/Bit-Day • Expected SRAM Upset Rate of <10-10 Errors/Bit-Day with

RTAX2000

Abstract: TB125 24mA-drive 352-Pin
Contextual Info: RTAX-S RadTolerant FPGAs Detailed Specifications Table 2-1 • I/O Features Comparison I/O Assignment Clamp Diode Hot Insertion 5V Tolerance Input Buffer Output Buffer LVTTL No Yes No Enabled/Disabled 3.3V PCI Yes No Yes1 Enabled/Disabled LVCMOS2.5V No Yes

RTAX2000

Abstract: footprint cqfp 280 RTAX1000S actel cqfp 84
Contextual Info: A dv an c ed v0 .5 RTAX-S RadTolerant FPGAs Designed for Space • • • • • • • • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETth > 60 MeV-cm2/mg – SEU Rate < 10-10 Errors/Bit-Day in Worst-Case

56 pin edac connector

Abstract: PCB footprint cqfp 132 Silicon Sculptor II ACTEL CCGA 624 mechanical
Contextual Info: v2.0 RTAX-S RadTolerant FPGAs Designed for Space • • • • • • • • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg – SEU Rate < 10-10 Errors/Bit-Day in Worst-Case

RTAX2000

Abstract: rtax4000 CDB 455 C34 IO358 DIODE SMD V05 128X3
Contextual Info: v5.1 RTAX-S/SL RadTolerant FPGAs Radiation Performance Leading-Edge Performance • • • • • • • • • • SEU-Hardened Registers Eliminate the Need for TripleModule Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg

4x4 matrix keypad in pic with c code

Abstract: keypad 4x4 c code for pic 4x4 matrix keypad and microcontroller lsd 3010 so do keyboard 4x4 pic datasheet for 4x4 keyboard 4x4 keypad to bcd ULN2003 led display datasheet keypad 4x4 c code for pic ULN2003 current buffer
Contextual Info: M AN557 Four Channel Digital Voltmeter with Display and Keyboard Author: MULTIPLEXING FOUR 7-SEGMENT LED DISPLAYS Stan D’Souza Microchip Technology Inc. Hardware INTRODUCTION The PIC16C71&#39;s I/O ports have an improved sink/source specification. Each I/O pin can sink up to

4x4 matrix keypad dspic

Abstract: 4x4 matrix keypad and microcontroller AN552 intcon 110B 16C71 180B PIC16C71 for 4x4 keypad to pic
Contextual Info: M AN552 Implementing Wake-up on Key Stroke Author: Stan D’Souza Microchip Technology Inc. INTRODUCTION Microchip's PIC16CXXX microcontroller family are ideally suited to directly interface to a keypad. The high 4-bits of PORTB RB7:RB4 have internal pull-ups and

RTAX1000SL

Abstract: RTAX1000S RTAX1000S-SL RTAX250SL RTAX2000SL RTAX2000S RTAX250S RTAX4000S 56 pin edac connector
Contextual Info: RTAX-S/SL RadTolerant FPGAs Detailed Specifications Table 2-1 • I/O Features Comparison I/O Assignment 3.3 V LVTTL Clamp Diode Hot Insertion / Cold Sparing 1 Yes 5V Tolerance Input Buffer Output Buffer No 1 Yes Enabled/Disabled Enabled/Disabled 3.3 V PCI

mc68hc05l11

Abstract: Nippon capacitors mc14151 BM 00362
Contextual Info: MC68HC05L11D/H MC68HC05L11 TECHNICAL DATA M O T O R O L A MOTOROLA SEMICONDUCTOR APPLICATION NOTE Designing with the MC68HC05L11 Data Flow for DDIR=1 in LCD Interface When designing with the MC68HC05L11, please note the following on the silicon with mask set

7 segment display 4x4 keyboard

Abstract: P16C71 lsd 3010 AN557 PIC16C71 ULN2003 keypad 4x4 7 segment display 4 digit segment led display 30 pin 00C-2 4 x 7-segment LED display module
Contextual Info: M AN557 Four Channel Digital Voltmeter with Display and Keyboard Author: MULTIPLEXING FOUR 7-SEGMENT LED DISPLAYS Stan D’Souza Microchip Technology Inc. Hardware INTRODUCTION The PIC16C71&#39;s I/O ports have an improved sink/source specification. Each I/O pin can sink up to

PIC16CXXX

Abstract: remote code 4x4 matrix keypad and microcontroller AN552 PIC16CXX 110B 16C71 180B PIC16C71 B11110000
Contextual Info: M AN552 Implementing Wake-up on Key Stroke Author: Stan D’Souza Microchip Technology Inc. INTRODUCTION Microchip's PIC16CXXX microcontroller family are ideally suited to directly interface to a keypad. The high 4-bits of PORTB RB7:RB4 have internal pull-ups and

dunlop s 708

Abstract: PTI 30 040 ga AX125 AX2000 CS180 FG256 FG324 FG484 PQ208 M33 thermal fuse
Contextual Info: Advanced v1.5  Axcelerator Family FPGAs Le adi n g- E dg e P e rfo r ma nc e • • • • – Voltage-Referenced I/O Standards: GTL+, HSTL Class 1, SSTL2 Class 1 and 2, SSTL3 Class 1 and 2 – Registered I/Os with 64-bit Deep FIFO on Each Pin "PerPin FIFO"

bss84zx

Abstract: MA111CT-ND atx 300 power supply schematic case sm-8 sot-223 marking S3 amplifier p-MOSFET soft start 60v S3 marking DIODE trigger detracted BSS84ZXCT-ND DLA DIODE TOSHIBA
Contextual Info: ACPI Controllers for Advanced Computer Systems HIP6500BEVAL1, HIP6502BEVAL1 TM Application Note July 2000 AN9862.1 Author: Bogdan M. Duduman Introduction ➤ Connect the Input Power Supply The Advanced Configuration and Power Interface specification (ACPI; [1]), written by a consortium

56 pin edac connector

Abstract: RTAX1000 edac 96 pin edac connector 292 CCGA
Contextual Info: v2.1 RTAX-S RadTolerant FPGAs Designed for Space • • • • • • • • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg – SEU Rate < 10-10 Errors/Bit-Day in Worst-Case

DP U1

Abstract: IO317 AX1000
Contextual Info: Advanced v1.5  Axcelerator Family FPGAs Leading-Edge Performance • • • • – Voltage-Referenced I/O Standards: GTL+, HSTL Class 1, SSTL2 Class 1 and 2, SSTL3 Class 1 and 2 – Registered I/Os with 64-bit Deep FIFO on Each Pin "PerPin FIFO" – Hot-Swap Compliant I/Os (Except PCI)

CI R-Y 1028

Abstract: a gn 137
Contextual Info: Advanced v0.2  RTAX-S Family FPGAs Sp e ci a l F ea t ur es f o r Sp a ce • Up to 10,752 SEU Hardened Flip-Flops Eliminate Software TMR Necessity >LET th 37 LET, GEO SEU Rate <10-10 Errors/Bit-Day • Expected SRAM Upset Rate of <10-10 Errors/Bit-Day with

RTAX2000S-CQ352

Contextual Info: RTAX-S RadTolerant FPGAs Detailed Specifications Table 2-1 • I/O Features Comparison I/O Assignment LVTTL Clamp Diode Hot Insertion / Cold Sparing 5V Tolerance No Yes No Input Buffer Output Buffer Enabled/Disabled 1 3.3 V PCI Yes No Yes Enabled/Disabled

RTAX2000

Abstract: IDTQS32X2384 352-Pin
Contextual Info: Advanced v0.1  RTAX-S Family FPGAs Sp e ci a l F ea t ur es f o r Sp a ce • Up to 10,752 SEU Hardened Flip-Flops Eliminate Software TMR Necessity >LET th 37 LET, GEO SEU Rate <10-10 Errors/Bit-Day • Expected SRAM Upset Rate of <10-10 Errors/Bit-Day with

4x1K

Abstract: edac 96 pin edac connector footprint cqfp 132 833 T12
Contextual Info: Advanced v0.5 RTAX-S RadTolerant FPGAs Designed for Space • • • • • • • • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETth > 60 MeV-cm2/mg – SEU Rate < 10-10 Errors/Bit-Day in Worst-Case

AX1000

Abstract: n14132 SYNAPTICAD WAVEFORMER ax125c k7g4 diode AA16
Contextual Info: Advanced v1.1 Axcelerator Family FPGAs Le adi n g- E dg e P e rfo r ma nc e • • • • 350+ MHz System Performance 500+ MHZ Internal Performance High-Performance Embedded FIFOs 622Mb/s LVDS Capable I/Os S pe ci fi c at i on s • • • • • Up to 2 Million Equivalent System Gates

lsd 3010

Abstract: 4 hexadecimal to 7-segment LED display module 4 units 7-segment LED display module ULN2003 led display 3 x 4 keypad to 7 segment 3 units 7-segment LED display module 4x4 keypad to bcd ULN2003 current buffer Test Board ULN2003 2.2k Preset
Contextual Info: M AN557 Four Channel Digital Voltmeter with Display and Keyboard Author: MULTIPLEXING FOUR 7-SEGMENT LED DISPLAYS Stan D’Souza Microchip Technology Inc. Hardware INTRODUCTION The PIC16C71&#39;s I/O ports have an improved sink/source specification. Each I/O pin can sink up to

RTAX2000

Abstract: RTAX2000S RTAX1000SL rtax250 RTAX250SL RTAX4000SL RTAX1000 RTAX-S RTAX1000S-SL rtax250s
Contextual Info: Rev ision 13 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Radiation Performance Specifications • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeVcm2/mg – SEU Rate < 10-10 Errors/Bit-Day (worst case GEO)

ERO Electronic ECS

Abstract: IT129 AD29 AD30 PSB21911 PSB4596 pa-769 GP100H
Contextual Info: ICs for Communications PCI Interface for Telephony/Data Applications PITA-2 PSB 4610 Version 2.2 Preliminary Data Sheet 01.00 DS 1 PSB 4610 Revision History: Current Version: 01.00 Previous Version: PSB 4610 Version 2.1 12.99 Page Page (in previous (in current