HM514400BS7
Abstract: HM514400BLS7 HM514400BS-7 HM514400BS6 HM514400BZ7 HM514400BLTT7 HM514400BLS-6 HM514400BLS-7 HM514400BS-6 HM514400BZ8
Text: ADE-203-269A Z HM514400B/BL Series HM514400C/CL Series 1,048,576-word x 4-bit Dynamic Random Access Memory Rev. 1.0 Nov. 29, 1994 The Hitachi HM514400B/BL, HM514400C/CL are CMOS dynamic RAM organized 1,048,576word × 4-bit. HM514400B/BL, HM514400C/CL have realized higher density, higher performance
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ADE-203-269A
HM514400B/BL
HM514400C/CL
576-word
HM514400B/BL,
HM514400C/CL
576word
HM514400BS7
HM514400BLS7
HM514400BS-7
HM514400BS6
HM514400BZ7
HM514400BLTT7
HM514400BLS-6
HM514400BLS-7
HM514400BS-6
HM514400BZ8
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IC 741 OPAMP
Abstract: SAA 1251 7106CPL TDA2620 SAA1121 LM 4440 AUDIO AMPLIFIER CIRCUIT touch dimmer TC 306H TDA 2310 TDA 2060 7107CPL
Text: Lineaire IC’s Lineaire IC’s dil to 99 dil 8 to 99 dil 18 to 78 to 99 dil 20 to 99 cer dip to 78 Wij leveren een groot aantal lineaire ic's uit voorraad. Kunt u een bepaald type niet vinden, aarzel dan niet ons telefonisch te raadplegen. Veelal kunnen wij u op korte
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fast page mode dram controller
Abstract: MT4C4001J
Text: MT4C4001J 883C 1 MEG x 4 DRAM AUSTIN SEMICONDUCTOR, INC. DRAM 1 MEG x 4 DRAM FAST PAGE MODE AVAILABLE AS MILITARY SPECIFICATIONS PIN ASSIGNMENT Top View • SMD 5962-90847 • MIL-STD-883 FEATURES • Industry standard x4 pinout, timing, functions and packages
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MT4C4001J
MIL-STD-883
100ns
120ns
300mW
D5000019
fast page mode dram controller
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PDF
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CY62157
Abstract: CY62157CV30 CY62157CV33
Text: CY62157CV30/33 512K x 16 Static RAM Features significantly reduces power consumption by 80% when addresses are not toggling. The device can also be put into standby mode reducing power consumption by more than 99% when deselected CE1 HIGH or CE2 LOW or both BLE and
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CY62157CV30/33
I/O15)
CY62157CV30:
CY62157CV33:
CY62157CV30
CY62157CV33
CY62157CV25
CY62157
CY62157CV30
CY62157CV33
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CY62157CV30
Abstract: CY62157CV33
Text: CY62157CV30/33 512K x 16 Static RAM Features significantly reduces power consumption by 80% when addresses are not toggling. The device can also be put into standby mode reducing power consumption by more than 99% when deselected CE1 HIGH or CE2 LOW or both BLE and
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CY62157CV30/33
I/O15)
CY62157CV30:
CY62157CV33:
CY62157CV30
CY62157CV33
CY62157CV25
CY62157CV30
CY62157CV33
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HM6216255H
Abstract: HM6216255HJP-10 HM6216255HJP-12 HM6216255HJP-15 HM6216255HLJP-10 HM6216255HLJP-12 HM6216255HLJP-15 HM6216255HTT-10 HM6216255HTT-12 Hitachi DSA00189
Text: HM6216255H シリーズ 4M high Speed SRAM 256-kword x 16-bit ADJ-203-269B (Z) ’98. 9. 15 Rev. 1.0 概要 HM6 21 62 55 H シリーズは 25 6k ワード×16 ビット構成の 4M ビット高速スタティック RAM です。CMOS （4 トランジスタ+2 ポリレジスタメモリセル）プロセス技術を採用し，高密度，高性能，低消費電力を実
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HM6216255H
256-kword
16-bit)
ADJ-203-269B
400-mil
10/12/15ns
200/180/160mA
70/60/50mA
HM6216255H
HM6216255HJP-10
HM6216255HJP-12
HM6216255HJP-15
HM6216255HLJP-10
HM6216255HLJP-12
HM6216255HLJP-15
HM6216255HTT-10
HM6216255HTT-12
Hitachi DSA00189
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Untitled
Abstract: No abstract text available
Text: QS88180, ô QS88160 High-Speed CMOS Dual 4Kx16/18 SRAM with Latched Addresses QS88180 QS88160 Preliminary FEATURES/BENEFITS • • • • • Dual 4Kx18/16 allows 2-way set associative cache Byte enables for byte/word read/write 20ns/25 ns/30ns/35 ns Taa commercial
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QS88180,
QS88160
4Kx16/18
QS88180
4Kx18/16
20ns/25
ns/30ns/35
ns/30ns/35/45
MIL-STD-883,
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A011 transistor
Abstract: No abstract text available
Text: QS88180, QS88160 High-Speed CMOS Dual 4Kx16/18 SRAM with Latched Addresses Q 7 QS88180 Q S88160 Preliminary FEATURES/BENEFITS • • • • • Dual 4Kx18/16 allows 2-way set associative cache Byte enables 1or byte/word read/write 20ns/25 ns/30ns/35 ns Taa commercial
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OCR Scan
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QS88180,
QS88160
4Kx16/18
QS88180
S88160
4Kx18/16
20ns/25
ns/30ns/35
ns/30ns/35/45
MIL-STD-883,
A011 transistor
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AEB DP1
Abstract: 0588 82385 A12A D815
Text: Q S88180, Q QS88160 High-Speed CMOS Dual 4Kx16/18 SRAM with Latched Addresses QS88180 Q S 88160 Prelim inary FE A T U R E S /B E N E FIT S • • • • • Dual 4Kx18/16 allows 2-way set associative cache Byte enables for byte/word read/write 20ns/25 ns/30ns/35 ns Taa commercial
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OCR Scan
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QS88180,
QS88160
4Kx16/18
QS88180
QS88160
4Kx18/16
20ns/25
ns/30ns/35
ns/30ns/35/45
MIL-STD-883,
AEB DP1
0588
82385
A12A
D815
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PDF
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taa 611 b12
Abstract: TAA611B12 TAA611B gv 273 TAA611 TAA611-B12 gv 271 611b schematic diagram power amplifier free 2 x 1w audio amplifier circuit diagram
Text: L I N E AR I N T E G R A T E D C I R C U I T TAA 611B AUDIO AMPLIFIER • • • • OUTPUT POWER 2.1 W 12 V - 8 f i LOW DISTORTION LOW QUIESCENT CURRENT HIGH INPUT IMPEDANCE The T A A 6 1 1 B is a m on olithic integrated c irc u it in a 14-lead quad in -lin e plastic
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OCR Scan
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TAA611B
14-lead
VS-12V
iiF/25V
taa 611 b12
TAA611B12
gv 273
TAA611
TAA611-B12
gv 271
611b
schematic diagram power amplifier free
2 x 1w audio amplifier circuit diagram
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4218160-60
Abstract: NEC 4218160 TI42 upd4218160 NEC A2C MARKING LE50 PD4218160 IR35-207 4218160
Text: DATA SHEET NEC MOS INTEGRATED CIRCUIT /¿PD42S18160,4218160 16M-BIT DYNAMIC RAM 1 M-WORD BY 16-BIT, FAST PAGE MODE, BYTE READ/WRITE MODE Description The ¿tPD42S18160, 4218160 are 1,048,576 words by 16 bits CMOS dynamic RAMs. The fast page mode and byte read/write mode capability realize high speed access and low power consumption.
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OCR Scan
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uPD42S18160
uPD4218160
16M-BIT
16-BIT,
tPD42S18160,
PD42S18160
50-pin
42-pin
MPD42S18160-60,
VP15-207-2
4218160-60
NEC 4218160
TI42
NEC A2C
MARKING LE50
PD4218160
IR35-207
4218160
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MC-424000F32F-60
Abstract: MC424000F32B60 mc424000f32 MC-424000F32B-60
Text: DATA SHEET NEC / MOS INTEGRATED CIRCUIT MC-424000F32 4M -W O RD BY 32-BIT DYNAMIC RAM MODULE HYPER PAGE MODE EOO D e s c rip tio n The MC-424000F32 is a 4,194,304 words by 32 bits dynamic RAM module on which 8 pieces of 16 M DRAM: /jPD4217405 are assembled.
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OCR Scan
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MC-424000F32
32-BIT
MC-424000F32
uPD4217405
MC-424000F32-60
MC-424000F32-70
72B-50A54
MC-424000F32F-60
MC424000F32B60
mc424000f32
MC-424000F32B-60
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UP17L
Abstract: No abstract text available
Text: November 1990 Edition 3.0 DATA SHEET : FUJITSU M B 8 1 C 1 0 0 0 A - 60/-70/-80/-10 CMOS 1,048,576 BIT FAST PAGE MODE DYNAMIC RAM CMOS 1M x 1 Bit Fast Page Mode DRAM The Fujitsu MB81C1000A is a CMOS, fully decoded dynamic RAM organized as 1,048,576 words x 1 bit. The MB81C1000A has been designed for mainframe
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OCR Scan
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MB81C1000A
Access1000A-70
MB81C1000A-80
MB81C1000A-10
MB81C1000A-60
MB81C1OO0A-70
UP17L
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Untitled
Abstract: No abstract text available
Text: NEC MOS INTEGRATED CIRCUIT juPD42S16805L, 4216805L 3.3 V OPERATION 16 M-BIT DYNAMIC RAM 2 M-WORD BY 8-BIT, HYPER PAGE MODE Description The /¿PD42S16805L, 4216805L are 2 097 152 words by 8 bits dynamic CMOS RAMs w ith optional hyper page mode. Hyper page mode is a kind o f the page mode and is useful fo r the read operation.
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OCR Scan
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juPD42S16805L
4216805L
PD42S16805L,
4216805L
28-pin
/iPD42S16805L-A60,
4216805L-A60
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APC UPS CIRCUIT DIAGRAM rs 1500
Abstract: APC UPS es 500 CIRCUIT DIAGRAM APC UPS 650 CIRCUIT DIAGRAM schematic diagram APC back ups XS 1000 TAA550 APC UPS CIRCUIT DIAGRAM UPS APC rs 1000 CIRCUIT diagram UPS APC rs 800 CIRCUIT diagram APC Back ES 500 UPS circuit diagram CIRCUIT DIAGRAM APC UPS 700
Text: 1 2 AF106 G E R M A N IU M MESA PNP VHF MIXER/OSCILLATOR The AF 106 is a germanium mesa PNP transistor in a Jedec TO-72 metal case. It Is particularly designed for use as preamplifier mixer and oscillator up to 260 MHz. ABSOLUTE MAXIMUM RATINGS ^CBO VcEO ^EBO
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AF106
AF106
APC UPS CIRCUIT DIAGRAM rs 1500
APC UPS es 500 CIRCUIT DIAGRAM
APC UPS 650 CIRCUIT DIAGRAM
schematic diagram APC back ups XS 1000
TAA550
APC UPS CIRCUIT DIAGRAM
UPS APC rs 1000 CIRCUIT diagram
UPS APC rs 800 CIRCUIT diagram
APC Back ES 500 UPS circuit diagram
CIRCUIT DIAGRAM APC UPS 700
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TCA 290
Abstract: No abstract text available
Text: LG Semicon 16Mx4.8Mx8 Base EDO DIMM Timing tu e \x i t* A S RAS . 1 tCSH r v tC K f tKSH tltCD tCAS CAS t i l A l. tRAH U sC tCAH > ADDRESS m m m tRKH itoi tKCS WE m tCAC to r ÎA A High-Z Ì D out tRAC m m > D a rt tofez tnzc D in m tcDD High-Z to z o
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OCR Scan
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16Mx4
TCA 290
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tractel
Abstract: s8m9
Text: •HYUNDAI HY51V4400B Series 1M X 4-bit CMOS DRAM PRELIMINARY DESCRIPTION The HY51V4400B is the new generation and fast dynamic RAM organized 1,048,576 x 4-bit. The HY51V4400B utilizes Hyundai's CMOS silicon gate process technology as well as advanced circuit techniques to provide wide
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OCR Scan
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HY51V4400B
TTL0/26
1AC12-00-MAY94
HY51V4400BJ
HY51V4400BU
HY51V4400BSU
tractel
s8m9
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nec hyper
Abstract: No abstract text available
Text: DATA SHEET NEC MOS INTEGRATED CIRCUIT JU P D 4 2 1 6 1 6 5 16 M BIT DYNAMIC RAM 1 M-WORD BY 16-BIT, HYPER PAGE MODE, BYTE READ/WRITE MODE Description The /¿PD4216165 is a 1 048 576 w o rd s by 16 b its d yn a m ic CMOS RAM w ith o p tio n a l h yp e r page m ode.
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OCR Scan
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16-BIT,
uPD4216165
/zPD4216165
50-pin
42-pin
cycles/64
/iPD4216165-50
/iPD4216165-60
PD4216165-70
20too§
nec hyper
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Untitled
Abstract: No abstract text available
Text: PRELIMINARY CMOS DRAM KM44V16000, KM44V16100 1 6 M x 4 B i t CM O S Dynamic RAM with Fast Page Mode DESCRIPTION This is a family of 16,777,216 x 4 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells within the same row. Refresh cycle 4K Ref. or 8K Ref. , access time(-5, -6,
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OCR Scan
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KM44V16000,
KM44V16100
16Mx4
KM44V16000
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PDF
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Untitled
Abstract: No abstract text available
Text: TS281-A89Z Decem ber 1989 FUJITSU DATA SHEET MB82B81-15/-20 256K BIT HIGH SPEED BI-CMOS SRAM 262,144-WORD x 1-BIT Bi-CMOS HIGH SPEED STATIC RANDOM ACCESS MEMORY The Fujitsu MB82B81 is a 65,536 words by 1 bits static random access memory fabricated with a CMOS silicon gate process. To make power dissipation lower and high speed, peripheral
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OCR Scan
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TS281-A89Z
MB82B81-15/-20
144-WORD
MB82B81
300mil
MB82B81-15
MB82B81-20
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PDF
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27S40
Abstract: Am27S40
Text: Am27S40/S41 Am 27S40/S41 4096 x 4 Bit Generic Series Bipolar IMOX PROM with ultra fast access time DISTINCTIVE CHARACTERISTICS Ultra fast access time " A " version (35ns max) — Fast access time Standard version (50ns max) — allow tremendous system speed improvements
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OCR Scan
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Am27S40/S41
27S40/S41
Am27S40A
Am27S41A
Am27S40
Am27S41
02122B
27S40
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PDF
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Untitled
Abstract: No abstract text available
Text: PRELIMINARY CMOS DRAM KM44V16000, KM44V16100 1 6 M x 4 B i t CMOS Dynamic RAM with Fast Page Mode DESCRIPTION This is a family of 16,777,216 x 4 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells within the same row. Refresh cycle 4K Ref. or 8K Ref. , access time(-5, -6,
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OCR Scan
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KM44V16000,
KM44V16100
16Mx4
0G2G371
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PDF
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UPD4216805L
Abstract: No abstract text available
Text: NEC MOS INTEGRATED CIRCUIT j u P D 42S 16805L , 4 2 1 6 8 0 5 L 3.3 V OPERATION 16 M BIT DYNAMIC RAM 2 M-WORD BY 8-BIT, HYPER PAGE MODE D escription The //PD42S16805L, 4216805L are 2 097 152 words by 8 bits dynamic CMOS RAMs w ith optional hyper page mode.
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OCR Scan
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uPD42S16805L
uPD4216805L
PD42S16805L,
4216805L
28-pin
//PD42S16805L-A60,
4216805L-A60
PD42S16805L-A70,
4216805L-A70
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001107
Abstract: No abstract text available
Text: DATA SHEET NEC MOS INTEGRATED CIRCUIT /¿ P D 42S 16405L , 4216405L 3.3 V OPERATION 16 M-BIT DYNAMIC RAM 4 M-WORD BY 4-BIT, HYPER PAGE MODE EDO D e s c rip tio n T h e/iP D 42S 16 405L , 4216405L a re 4 ,1 94,304 words by 4 bits CMOS dynam ic RAM with optional hyper page mode
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OCR Scan
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16405L
4216405L
uPD42S16405L
uPD4216405L
PD42S16405L
16405L,
4216405L
26-pin
VP15-207-2
001107
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PDF
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