T60T Search Results

H20-080

Contextual Info: Low Inductance Chip Capacitors Typical Performance Curves 240 160 200 180 T60T 160 140 120 60 20 50 70 Figure 6 – Typical Temperature Characteristics of LICA Dielectrics Using 25V Single Capacitor 25V 80 80 10 30 Temperature, °C Impedance 5V 10V 100

diode T35 12H

Abstract: ST10F269Z2Q6 ST10F269Q ST10F269Z2T3 PQFP144 ST10F269 TQFP144 diode t318 BB126 st10 Bootstrap
Contextual Info: ST10F269 16-BIT MCU WITH MAC UNIT, 128K to 256K BYTE FLASH MEMORY AND 12K BYTE RAM DATASHEET • ■ 2K Byte Internal RAM 16 CPU-Core and MAC Unit Watchdog 16 10K Byte XRAM CAN1_RXD CAN1_TXD CAN1 CAN2_RXD CAN2_TXD CAN2 PEC Oscillator and PLL 16 Interrupt Controller

GPR circuit schematic diagram full

Abstract: DP43 T308 ST10F269-T6 ST*10f269-q3 m29F ST10F269-T3 TQFP144 f082h st10 Bootstrap
Contextual Info: ST10F269-T3 16-BIT MCU WITH MAC UNIT, 256K BYTE FLASH MEMORY AND 12K BYTE RAM March 2003 FAIL-SAFE PROTECTION – PROGRAMMABLE WATCHDOG TIMER – OSCILLATOR WATCHDOG • ■ ON-CHIP BOOTSTRAP LOADER CLOCK GENERATION – ON-CHIP PLL – DIRECT OR PRESCALED CLOCK INPUT

GPR circuit schematic diagram full

Abstract: ST10F269Z2q3 PQFP144 ST10 ST10F269 03 T48 regulator st10 Bootstrap
Contextual Info: ST10F269Z2Qx 16-BIT MCU WITH MAC UNIT, 256K BYTE FLASH MEMORY AND 12K BYTE RAM PRELIMINARY DATA August 2002 • ■ 16 32 256K Byte Flash Memory 2K Byte Internal RAM 16 CPU-Core and MAC Unit Watchdog 16 10K Byte XRAM PEC Oscillator and PLL CAN1_RXD CAN1_TXD

st10f276 jtag

Abstract: w1p 59 ST10F276 st10 Bootstrap EF52 transistor w2P w1p 83 W1P 76 transistor LQFP144 ST10
Contextual Info: ST10F276 16-bit MCU with MAC unit, 832 Kbyte Flash memory and 68 Kbyte RAM Features • ■ ■ ■ ■ ■ Highly performant 16-bit CPU with DSP functions – 31.25ns instruction cycle time at 64MHz max CPU clock – Multiply/accumulate unit MAC 16 x 16-bit

capacitor 100nf 25v 0805 datasheet

Abstract: LU 2705 0805 10V X7R 1,5 nF 1206 0.22 ohm C 12 PH diode capacitor 47 nano capacitor 100nf 50v 0805 datasheet capacitor x2 ceramic capacitor 100nF 104 ELCO 2.2 16v
Contextual Info: AVX Low Inductance Capacitors Low Inductance Chip Capacitors Introduction As switching speeds increase and pulse rise times decrease the need to reduce inductance becomes a serious limitation for improved system performance. Even the decoupling capacitors, that act as a local energy source, can generate

Contextual Info: 5 ,993 MflY r z j S G S -m 0 M S 0 N l^ 0 g [ E ] [ l[ L il T O K ! ] 0 © i S T 1 0 F 1 6 6 16 BIT MCU WITH 256K FLASH MEMORY AND A/D CONVERTER ADVANCE DATA High-Perform snce 16-bit CPU with 4-Stage Pipeline 100 ns Instruction Cycle Time at 20 MHz CPU

Contextual Info: SCS-THOMSON *JM > DSll g|g@ilUl inMID @ ST10R163 16-BIT ROMLESS MICROCONTROLLER DATASHEET High performance 16-bit CPU with 4-stage pipeline 80ns instruction cycle time at 25-MHz CPU clock 400 ns multiplication (16 x 16 bits , 800 ns division (32 /1 6 bit)

Contextual Info: / IT G S-1 H 0 M S0 N #. SIMOtg^lULKgìfMnigg_ ST10R163 16-BIT ROMLESS MICROCONTROLLER D ATASH EET • High performance 16-bit CPU with 4-stage pipeline ■ 80ns instruction cycle time at 25-MHz CPU clock ■ 400 ns multiplication 16 x 16 bits , 800 ns

Contextual Info: C167 FAMILY PRELIMINARY USER MANUAL C167 FAMILY PRELIMINARY USER MANUAL USE IN LIFE SUPPORT DEVICES OR SYSTEMS MUST BE EXPRESSLY AUTHORIZED SG S-TH O M SO N PRO DUCTS ARE NOT AUTHO RIZED FOR USE AS CR ITICAL CO M PO NENTS IN LIFE SUPPO RT DEVICES OR SYSTEM S W ITH O U T THE EXPRESS W RITTEN APPRO VAL OF SG S-THOM SO N

Contextual Info: ST10F167 16-bit MCU with 128KByte FLASH memory DATASHEET High Performance CPU • 16-bit CPU with 4 stage pipeline • 100ns instruction cycle time at 20MHz CPU clock • 500ns multiplication 16*16 bit • 1(as division (32/16 bit) • Enhanced boolean bit manipulation

ST10

Abstract: ST10R172L st10 Bootstrap
Contextual Info: ST10R172L 16-BIT LOW VOLTAGE ROMLESS MCU DATASHEET • High Performance 16-bit CPU ● ● ● ● ● ● ● ● ■ ● ● ● ● ● OSC WDT Programmable external bus characteristics for different address ranges 8-bit or 16-bit external data bus Multiplexed or demultiplexed external

ST10

Abstract: ST10F163 st10 Bootstrap
Contextual Info: ST10F163 16-BIT MCU WITH 128K BYTE FLASH MEMORY PRELIMINARY DATA • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Internal RAM Watchdog 16 Interrupt Controller PLL OSC. 16 16 8 Port 6 8 ■ ■ ■ ■ ■ ■ BRG Port 5 6 ASC usart ■

ST10

Abstract: ST10R165 T4836 st10 Bootstrap
Contextual Info: ST10R165 16-BIT ROMLESS MICROCONTROLLER DATASHEET • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ June 1997 Internal Ram Watchdog PEC Interrupt C ontroller 16 16 16 8 Port 6 GPT1 GPT2 Port 5 8 SSC ■ 16 16 ASC USART ■ CPU-Core

ST10

Abstract: ST10R172L st10 Bootstrap
Contextual Info: ST10R172L 16-BIT LOW VOLTAGE ROMLESS MCU PRODUCT PREVIEW • High Performance 16-bit CPU ● ● ● ● ● ● ● ● ■ ● ● ● ● ● OSC WDT Programmable external bus characteristics for different address ranges 8-bit or 16-bit external data bus

SUSCON capacitor

Abstract: ST10F168-Q3 transmitter circuit in GPR st10f168s SUSCON PQFP144 ST10F168 diode T35 12H st10 Bootstrap
Contextual Info: ST10F168 16-BIT MCU WITH 256K BYTE FLASH MEMORY AND 8K BYTE RAM HIGH PERFORMANCE CPU – 16-BIT CPU WITH 4-STAGE PIPELINE – 80ns INSTRUCTION CYCLE TIME AT 25MHz CPU CLOCK – 400ns 16 X 16-BIT MULTIPLICATION – 800ns 32 / 16-BIT DIVISION – ENHANCED BOOLEAN BIT MANIPULATION

SERVICE MANUAL tv TCL

Abstract: 105mS 143 tgg PQFP144 ST10F167 cm 20 mdl 12h 7 segment HS 1106 BS st10 Bootstrap si2761
Contextual Info: ST10F167 16-BIT MCU W ITH 128KBYTE FLASH M EM O RY • HIGH PER FO R M AN C E CPU - 1 6 - B IT CPU W IT H 4-STAG E PIPELINE. - 1 6 - B IT CPU W IT H 4 S T A G E PIPELINE - 1 0 0 N S INSTRUCTIO N CYC LE TIM E AT 20M Hz CPU CLOCK - 5 0 0 N S M ULTIPLICATIO N 16*16 BIT

Contextual Info: SIEMENS C16x-Family of High-Performance CMOS 16-Bit Microcontrollers C167SR Advance Information C167SR • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 16-Bit Microcontroller High Performance 16-bit CPU with 4-Stage Pipeline

st10 Bootstrap

Abstract: T03-15 ST10F269 03
Contextual Info: ST10F269 16-BIT MCU WITH MAC UNIT, 128K to 256K BYTE FLASH MEMORY AND 12K BYTE RAM DATASHEET • ■ 2K Byte Internal RAM 16 CPU-Core and MAC Unit Watchdog 16 10K Byte XRAM CAN1_RXD CAN1_TXD CAN1 CAN2_RXD CAN2_TXD CAN2 PEC Oscillator and PLL 16 Interrupt Controller

C100H

Abstract: PIN DIAGRAM of st10f280 EE30h st10 Bootstrap BUT16
Contextual Info: ST10F280 16-BIT MCU WITH MAC UNIT, 512K BYTE FLASH MEMORY AND 18K BYTE RAM PRODUCT PREVIEW • ON-CHIP BOOTSTRAP LOADER CLOCK GENERATION - ON-CHIP PLL. - DIRECT OR PRESCALED CLOCK INPUT. ■ UP TO 143 GENERAL PURPOSE I/O LINES - INDIVIDUALLY PROGRAMMABLE AS INPUT, OUTPUT OR SPECIAL FUNCTION.

ST10F269 03

Abstract: GPR circuit schematic diagram full PQFP144 ST10F269 ST10F269-Q3 st10 Bootstrap FE90
Contextual Info: ST10F269 16-BIT MCU WITH MAC UNIT, 256K BYTE FLASH MEMORY AND 12K BYTE RAM PRELIMINARY DATA • ■ ■ ■ 16 32 256K Byte Flash Memory 2K Byte Internal RAM 16 CPU-Core and MAC Unit Watchdog 16 10K Byte XRAM PEC Oscillator and PLL CAN1_RXD CAN1_TXD CAN1 CAN2_RXD

BCD 7SEGMENT

Abstract: digital clock with 7segment BCD to 7segment decoder 7SEGMENT 5 T523H 7segment all stk ic diagram c166 C programming PEC 302 PRESET 1MOHMS
Contextual Info: ST10R272L USER’S MANUAL Release 1.0 Table of Contents 1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 ARCHITECTURAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Contextual Info: ST10R167 16-BIT ROMLESS MCU • 16 32 ROMLESS 16 Internal RAM 16 CPU-Core PEC Watchdog 16 XRAM Interrupt Controller 16 OSC. 8 Port 6 8 Port 5 16 BRG BRG Port 3 15 Port 7 8 August 1999 This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

capacitor 10 MF 25v

Contextual Info: Low Inductance Chip Capacitors Low Inductance Chip Arrays LICA Also the effective current path length is minimized because the current does not have to travel the entire length of both electrodes to complete the circuit. This reduces the self inductance of the electrodes. The self inductance is also minimized by the fact that the charging current is supplied by