T004152 Search Results
T004152 Datasheets Context Search
Catalog Datasheet | Type | Document Tags | |
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734A coaxial cable
Abstract: 68 pin plcc socket view bottom D-C73C ebe switches TAIS SOT TXC-02021 step down transformer TR499
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44-pin 68-pin TXC-02020 44-Pin) TXC-02021 68-Pin) 734A coaxial cable 68 pin plcc socket view bottom D-C73C ebe switches TAIS SOT TXC-02021 step down transformer TR499 | |
Contextual Info: DJB Device Quad DS1 Dejitter Buffer TXC-03351 DATA SHEET Preliminary FEATURES = • = .■ : = • Reduces receive jitter on DS1 signals due to transmission and stuffing source jitter • Dejitters four DS1 signals • Satisfies Bellcore category I jitter requirements |
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TXC-03351 TXC-21002, T0041S2 | |
Contextual Info: MRT Device X co u w 6-, 8-, 34-Mbit/s Line Interface TXC-02050 DATA SHEET FEATURES DESCRIPTION ' = = The TranSwitch Multi-rate Receive/Transmit MRT device is a CMOS VLSI device that provides the func tions needed for terminating two CCITT line rates, 8448 |
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34-Mbit/s TXC-02050 TXC-02050-MB | |
Contextual Info: ART Devices ~>T~ z a o a Advanced DS3/STS-1 Receiver/Transmitter ART: TXC-02020 44-Pln ARTE: TXC-02021 (68-Pin) w DATA SHEET Preliminary maaa .= • Single device line interface for DS3 and STS-1 • Single +5V power supply • Meets ‘crossconnect frame’ mask requirements |
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TXC-02020 44-Pln) TXC-02021 68-Pin) TXC-02020-MB | |
Contextual Info: JT2F D evice 6 Mbit/s JT2 Framer TXC-03702B DATA SHEET Product Preview DESCRIPTION 11 = The JT2 Framer JT2F is a CMOS VLSI device that provides the functions needed to frame a wideband payload to ITU G.704 and the NTT-specified 6312 kbit/s frame format for ATM operation. The JT2F interfaces to |
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TXC-03702B TXC-21047B, RS-232 TXC-05150, 1DD4152 TXC-03702B-MB | |
Contextual Info: E2/E3F Device 8-, 34-Mbit/s Framer TXC-03701B DATA SHEET FEATURES DESCRIPTION • Framer for ITU-TSS Recommendations: - G.742 8448 kbit/s - G.745 (8448 kbit/s) - G.751 (34368 kbit/s) - G.753 (34368 kbit/s) The E2/E3 Framer (E2/E3F) is a CMOS VLSI device |
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34-Mbit/s TXC-03701B TXC-03701 | |
CH341A
Abstract: digital trainer schematic diagram laf 0001 CH3401 J0123 ccs ldl HP 3D6 000A75 X77H-X70H TO SI 788 48D
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FBE12-FBE8. TXC-03104-MB CH341A digital trainer schematic diagram laf 0001 CH3401 J0123 ccs ldl HP 3D6 000A75 X77H-X70H TO SI 788 48D | |
pe-67583
Abstract: hecs 50 ATM-25 Crystal Oscillator TXC PIN DIAGRAM on pad for RJ45 ALI-25 ALI-25C ALI-25T TXC-05501 TXC-07025
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ALI-25C ALI-25T TXC-07025 ATM-25 53-byte ALI-25 TXC-07025 TXC-07025-MB T0D41S2 pe-67583 hecs 50 Crystal Oscillator TXC PIN DIAGRAM on pad for RJ45 ALI-25T TXC-05501 | |
566 pin diagram
Abstract: 734A coaxial cable hp54502a hp3784A TAIS SOT TXC-02021 power combiner broadband transformers HP-3784A 10A ferrite bead b3-z
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44-pin 68-pin 102-1ubsection. TXC-02020-MB 566 pin diagram 734A coaxial cable hp54502a hp3784A TAIS SOT TXC-02021 power combiner broadband transformers HP-3784A 10A ferrite bead b3-z | |
Contextual Info: M13E Device DS3/DS1 MUX/DEMUX, Extended Features TXC-03303 DATA SHEET FEATURES - = " ~ . = • Multiplexes/demultiplexes 28 DS1 signals to/from a DS3 signal. • M13 or C-bit parity mode operation • FEBE, C, or P-bit parity error insertion capability • DS3 idle signal generators |
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TXC-03303 TXC-03303-MB 0030D | |
Contextual Info: STAF Device SONET/SDH Transceiver and Framer 622/155.5 Mbit/s TXC-02623 DATA SHEET Preliminary DESCRIPTION FEATURES Byte-parallel multiplexing, demultiplexing, fram ing, and clock synthesis PLL in one device = The STAF VLSI device is a SONET/SDH transceiver |
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TXC-02623 68-pin TXC-02623 T004152 D00120S TXC-02623-MB TXC-02623-ACCQ | |
DAX 3SContextual Info: L3M Device Level 3 Mapper TXC-03452 DATA SHEET Product Preview i—— = = = = = = = = = = • SDH/SONET bus access: -Drop/add data byte access with clock, C1J1, SPE, and parity -Add bus interface timing derived from drop bus, add bus, or external timing |
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TXC-03452 0G4152 TXC-03452-MB DAX 3S | |
Contextual Info: t r ä ^ s S w it c h P H A S T -1 D e v ic e SONET STS-1 Overhead Terminator TXC-06101 « DATA SHEET DESCRIPTION FEATURES Provides SONET interface to any type of payload Programmable STS-1 or STS-N modes Receive bit-serial STS-1 signal input to the Line Side using external reference frame pulse for |
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TXC-06101 Q00flb05 TXC-06101 TXC-06101-MB | |
Contextual Info: L4M Device Level 4 Mapper TXC-03456 DATA SHEET Preliminary . = • Maps an asynchronous 139.264 Mbit/s tributary into an AU-4/VC-4 STS-3c/SPE. • Nibble or byte 139.264 Mbit/s line interface - G.751 receive and transmit performance |
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TXC-03456 DM220 TXC-03456-MB | |
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Contextual Info: SM3 Device SONET 3:1 Mux/Demux TXC-02201 w w DATA SHEET FEATURES ; — DESCRIPTION • Multiplexes/demultiplexes three serial STS-1 signals from an STS-3 The SM3 is a CMOS VLSI device that provides the functions needed to multiplex and demultiplex three STS-1 signals to and from an STS-3 signal. The SM3 |
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TXC-02201 -26TO TXC-02201-MB | |
LOS13
Abstract: DR24 motor T2X6
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TXC-03303 T004152 LOS13 DR24 motor T2X6 | |
Contextual Info: COBRA Device Constant Bit Rate ATM Adaptation Layer 1 TXC-05427 FEATURES i , —- = DATA SHEET Product Preview = DESCRIPTION COBRA C o nstant Bit Bate ATM Adaptation Layer 1 is a four-channel VLSI device that implements all of the functions needed for circuit emulation over ATM. Both |
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TXC-05427 D002QS2 TXC-05427-MB | |
cdb 475 eContextual Info: CDB Device Cell Delineation Block TXC-05150 m W DATA SHEET Preliminary FEATURES DESCRIPTION • ATM cell delineation per CCITT I.432 • ATM cell rate adaptation • Identifies OAM F4 cells and non-user cells • Operation from 1.544 Mbps to 155.52 Mbps • Programmable interfaces to DS1, DS3, E1, E3, |
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TXC-05150 TXC-05150-MB cdb 475 e | |
Contextual Info: QDS1F Device QUAD DS1 Framer TXC-03102 DATA SHEET Preliminary = • D4 SF, ESF including FDL support , and transparent framing modes DESCRIPTION m ssg.ss=saam .i i = • Detects, counts and forces line code errors (BPVs and excess zeros), CRC errors (ESF |
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TXC-03102 TXC-05150, TDD41S2 0DD1473 TXC-03102-MB TXC-05427, TXC-06125, D001474 | |
Contextual Info: M13 Device DS3/DS1 MUX/DEMUX TXC-03301 DATA SHEET Preliminary FEATURES - ~ DESCRIPTION = = f ^ — The M13 is a CMOS VLSI device that provides the func tions needed to multiplex and demultiplex 28 indepen dent DS1 signals to and from a DS3 signal with either |
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TXC-03301 1D041S5 181-PGA | |
Contextual Info: SYN155C Device 155-Mbit/s Synchronizer Clock & Data Output TXC-02302B DATA SHEET FEATURES DESCRIPTION:. ' •Transm its and receives at S T S -3 /S T M -1 rates = T h e T ranS w itch S Y N 1 5 5 C synch ro nizer d evice provides a c o m p le te S T S -3 /S T M -1 fra m e synchronization function in a |
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SYN155C 155-Mbit/s TXC-02302B -27T0G4152 | |
Contextual Info: E123MUX Device E1/E2/E3 MUX/DEMUX TXC-03361 DATA SHEET PRODUCT PREVIEW = • Multiplexer/demultiplexer for ITU-T Recommendations: G.742 E2 frame format G.751 (E3 frame format) DESCRIPTION = The E123MUX is a CMOS VLSI device that provides the E13 functions needed to multiplex and demultiplex |
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E123MUX TXC-03361 E12/E23 E12RLm) E23RLm) D004b2Ã TXC-03361-MB | |
Contextual Info: SOT-3 Device STM-1 /STS-3/STS-3C Overhead Terminator TXC-03003 DATA SHEET Preliminary Full overhead"processing, corrpiant witn and CCITT standards a n s i' Transmit and receive pointer generation with respect to external clock and frame signals Byte-wide data, clock and frame on the line side |
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TXC-03003 TXC-21061, OT-3/SYN155/ADMA-E1 SYN155 RS-232 TXC-05501, TXC-05601, | |
JD 1801 PIN DIAGRAM
Abstract: RTCO Z511A epoch t14 12D1C-D ET 723 TAIS SOT TA-NWT-000253 s004152 0Q0043
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TXC-03001 RS-232 TXC-21011, 1DD41SS JD 1801 PIN DIAGRAM RTCO Z511A epoch t14 12D1C-D ET 723 TAIS SOT TA-NWT-000253 s004152 0Q0043 |