Z80180
Abstract: Zilog z180 Z8018233FSC Z80180 technical manual Z80182 ESCC technical manual z182 Z180 Z180 mpu Zilog 85230 z180 controller
Text: Zilog Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL P R E L I M I N A R Y P RELIMINARY P RODUCT S PECIFICATION Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL CONTROLLER ZIP FEATURES • Z8S180 MPU - Code Compatible with Zilog Z80 /Z180™ CPU - Extended Instructions
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Z80182/Z8L182
Z8S180
/Z180TM
16-Bit
32-Bit
100-Pin
DS971820600
PS009801-0301
Z80180
Zilog z180
Z8018233FSC
Z80180 technical manual
Z80182
ESCC technical manual z182
Z180
Z180 mpu
Zilog 85230
z180 controller
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Nx62
Abstract: DS3100 DS3104GN DS3104-SE GR-1244-CORE GR-253-CORE GR-499-CORE
Text: Rev: 072407 DS3104-SE Line Card Timing IC with Synchronous Ethernet Support General Description The DS3104-SE is a low-cost, feature-rich timing IC for line cards with synchronous Gigabit Ethernet GbE , 10-Gigabit Ethernet (10GbE), and Fast Ethernet ports.
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DS3104-SE
DS3104-SE
10-Gigabit
10GbE)
Nx62
DS3100
DS3104GN
GR-1244-CORE
GR-253-CORE
GR-499-CORE
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DS3100
Abstract: DS3105 DS3105LN GR-1244-CORE GR-253-CORE LQFP64 MCR10 ACS8525 MCR10 ROHS D1801
Text: Preliminary. Subject to Change Without Notice. PRELIMINARY DATASHEET DS3105 Line Card Timing IC www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS3105 is a low-cost, feature-rich timing IC for telecom line cards. Typically the device accepts two reference clocks from dual redundant system timing
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DS3105
DS3105
100Mb/s)
DS3100
DS3100
DS3105LN
GR-1244-CORE
GR-253-CORE
LQFP64
MCR10
ACS8525
MCR10 ROHS
D1801
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zct02
Abstract: SZ1 AMI
Text: P r e l im in a r y P r o d u c t S p e c if ic a t io n V % Z80185/Z80195 S m a r t P e r ip h e r a l C o n t r o l l e r s FEATURES • 0°C to +70°C Temperature Range ■ Enhanced Z8S180 MPU ■ Four Z80 CTC Channels 100-Pin QFP Package ■ One Channel ESCC” Controller
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Z80185/Z80195
Z80185
Z80195
512KB
Z8S180
100-Pin
Z80195
parall5/Z80195
zct02
SZ1 AMI
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Z08030, Z08530
Abstract: Z8523010VSC Z85230 Z8523010VEC Z8523016VEC ESCC technical manual IN SDLC PROTOCOL Z08030 Z8523020PSC M043
Text: Pr o d u c t S p e c if ic a t io n < £ 2 iL Œ Z85230 ESCC Enhanced S erial Com m unication Controller FEATURES • Deeper Data FIFOs - 4-Byte Transmit FIFO - 8-Byte Receive FIFO ■ Programmable FIFO Interrupt Levels Provide Flexible Interrupt Response
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Z85C30
Z85230
Z8523020PSC
Z8523020VSC
Z8523008PSC/PEC
Z8523008VSC/VEC
Z8523010PSC
Z8523010VSC
Z8523010PEC
Z08030, Z08530
Z85230
Z8523010VEC
Z8523016VEC
ESCC technical manual
IN SDLC PROTOCOL
Z08030
M043
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Untitled
Abstract: No abstract text available
Text: Rev: 120707 DS3105 Line Card Timing IC Features General Description The DS3105 is a low-cost, feature-rich timing IC for telecom line cards. Typically, the device accepts two reference clocks from dual redundant system timing cards. The DS3105 continually monitors both inputs
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DS3105
100Mbps)
400Hz
DS3105
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nx10 alarm system
Abstract: nx10 alarm
Text: Preliminary. Subject to Change Without Notice. PRELIMINARY DATASHEET DS3102 Stratum 3 Timing Card IC with Synchronous Ethernet Support www.maxim-ic.com GENERAL DESCRIPTION FEATURES When paired with an external TCXO or OCXO, the DS3102 is a highly integrated central timing and
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DS3102
DS3102
GR1244,
GR-253,
DS3100
nx10 alarm system
nx10 alarm
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Untitled
Abstract: No abstract text available
Text: Rev: 070308 DS3102 Stratum 3 Timing Card IC with Synchronous Ethernet Support General Description The DS3102 is a low-cost, feature-rich timing IC for telecom timing cards. With 8 input clocks, the device directly accepts both line timing from a large number of
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DS3102
GR-1244,
GR-253,
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Untitled
Abstract: No abstract text available
Text: Rev: 012108 DS3102 Stratum 3 Timing Card IC with Synchronous Ethernet Support Features General Description The DS3102 is a low-cost, feature-rich timing IC for telecom timing cards. With 8 input clocks, the device directly accepts both line timing from a large number of
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DS3102
GR-1244,
GR-253,
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Z8030ACS
Abstract: Z8030APS Z8030A IN SDLC PROTOCOL USING SCC WITH Z8000 IN SDLC PROTOCOL CRC-16 Z8000 Z8030 z-scc Z8030 PS
Text: Z8030 Z8000 Z-SCC Serial Communications Controller Product Specification Zilog A pril 1985 • Two in dependent, 0 to 1.5M bit/second, fullduplex channels, eac h with a separate crystal oscillator, b a u d rate generator, a n d Digital Phase-L ocked Loop for clock recovery.
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Z8030
Z8000Â
Z8030A
44-pin
Z8030AVS
40-pin
Z8030ACS
Z8030APS
IN SDLC PROTOCOL
USING SCC WITH Z8000 IN SDLC PROTOCOL
CRC-16
Z8000
z-scc
Z8030 PS
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PS011701-0701
Abstract: No abstract text available
Text: Z80C30/Z85C30 CMOS SCC Serial Communications Controller Product Specification PS011701-0701 ZiLOG Worldwide Headquarters • 910 E. Hamilton Avenue • Campbell, CA 95008 Telephone: 408.558.8500 • Fax: 408.558.8300 • www.ZiLOG.com This publication is subject to replacement by a later edition. To determine whether
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Z80C30/Z85C30
PS011701-0701
Z80C30/Z85C30
Z80C3008PSC
Z80C3008VSC
Z85C3008PSC/PEC
Z85C3008VSCNEC
Z80C3010PSC
Z80C3010VSC
Z85C3010PSC/PEC
PS011701-0701
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Untitled
Abstract: No abstract text available
Text: Zilog Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL P R E L I M I N A R Y P RELIMINARY P RODUCT S PECIFICATION Z80182/Z8L182 ZILOG I NTELLIGENT PERIPHERAL CONTROLLER ZIP FEATURES • Z8S180 MPU - Code Compatible with Zilog Z80 /Z180™ CPU - Extended Instructions
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Z80182/Z8L182
Z8S180
/Z180â
16-Bit
32-Bit
100-Pi.
DS971820600
PS009801-0301
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PDF
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VL8530
Abstract: IN SDLC PROTOCOL NMOS8530 VL85C35-04CC VL85C35-04PC VL85C35-04QC VL85C35-06CC VL85C35-06PC VL85C35-06QC til 312
Text: VL85C35 ? o' ENHANCED SERIAL COMMUNICATIONS CONTROLLER ESCC FEATURES DESCRIPTION • The VLB5C35 CMOS Enhanced Serial Communications Controller (ESCC) is a dual-channel, multi-protocol data communications peripheral designed for use with non-multiplexed buses.
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VL85C35
14-bit
19-bit-wide
NMOS8530
VLB5C35
VL8530
IN SDLC PROTOCOL
NMOS8530
VL85C35-04CC
VL85C35-04PC
VL85C35-04QC
VL85C35-06CC
VL85C35-06PC
VL85C35-06QC
til 312
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thomson RT 463 Schematic
Abstract: Z8530 F 0513A fli5 WR1 marking code IN SDLC PROTOCOL PLCC44 RR15 WR10 ZS330
Text: SGS-THOMSON Z8530 SERIAL COMMUNICATIONS CONTROLLER Thank you for your interest in the SCC, one of the most versatile and most popular Serial Data Com munications ICs. This document is intended to pro vide answers to all technical questions about the Z8530 Serial Communications Controller. Please
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Z8530
Z8530
CDIP-40
Z8530AD6N
Z8530AD2N
Z8530AC1V
PLCC44
Z8530AC6V
thomson RT 463 Schematic
F 0513A
fli5
WR1 marking code
IN SDLC PROTOCOL
PLCC44
RR15
WR10
ZS330
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Untitled
Abstract: No abstract text available
Text: Pr o d u c t S p e c if ic a t io n < £ 3 L0 E Z85230 E S C C E n h a n c e d S e r ia l C o m m u n ic a t io n C o n t r o l l e r FEATURES • Deeper Data FIFOs - 4-Byte Transm it FIFO - 8-Byte Receive FIFO ■ Program m able FIFO Interrupt Levels Provide Flexible
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Z85230
Z8523008PSC/PEC
Z8523008VSC/VEC
Z8523010PSC
10VSC
Z8523010PEC
Z8523010VEC
16PSC
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TCXO 30.72MHz
Abstract: 30.72MHZ oscillator 0.02PPM 3.3 TCXO 24.576 ACS8525 DS3100 DS3105 DS3105LN GR-1244-CORE GR-253-CORE MCR10
Text: 19-4628; Rev 3; 5/09 DS3105 Line Card Timing IC Features General Description The DS3105 is a low-cost, feature-rich timing IC for telecom line cards. Typically, the device accepts two reference clocks from dual redundant system timing cards. The DS3105 continually monitors both inputs
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DS3105
DS3105
100Mbps)
400Hz
TCXO 30.72MHz
30.72MHZ oscillator 0.02PPM 3.3
TCXO 24.576
ACS8525
DS3100
DS3105LN
GR-1244-CORE
GR-253-CORE
MCR10
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ACS8522
Abstract: 10mhz OCXO Digital Alarm Clock by ttl DS3102 DS3102GN GR-1244 GR-1244-CORE GR-253 GR-253-CORE
Text: 19-4617; Rev 5; 8/10 DS3102 Stratum 2/3E/3 Timing Card IC with Synchronous Ethernet Support General Description The DS3102 is a low-cost, feature-rich timing IC for telecom timing cards. With 8 input clocks, the device directly accepts both line timing from a large number of
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DS3102
DS3102
GR-1244,
GR-253,
GR-1244-compliant
ACS8522
10mhz OCXO
Digital Alarm Clock by ttl
DS3102GN
GR-1244
GR-1244-CORE
GR-253
GR-253-CORE
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transistor marking WR5 72
Abstract: txc xtal sdlc ibm signals z8030 DDR14
Text: < 2 > 2 iL G E Pr o d u c t S p é c if ic a t io n Z16C35/Z85C35 CMOS ISC C INTEGRATED SERIAL C o m m u n ic a t io n s C o n t r o l l e r FEATURES • Two general-purpose SCC channels, four DMA channel; and a Universal Bus Interface Unit. ■ Software compatible to the Zilog CMOS SCC
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Z16C35/Z85C35
680x0
32-bit
16-pin
Z16C35
transistor marking WR5 72
txc xtal
sdlc ibm signals
z8030
DDR14
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Z8523016VEC
Abstract: Z8523016vsc Z8523016PEC Z8523008VSC z8523010vsc Z8523020PSC z85230 z08030
Text: i £ S L C E P r o d u c t S p e c if ic a t io n Z85230 ESCC ENHANCED S E R IA L C o m m u n ic a t io n C o n t r o l l e r FEATURES • Deeper Data FIFOs - 4-Byte Transmit FIFO - 8-Byte Receive FIFO ■ Programmable FIFO Interrupt Levels Provide Flexible
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Z85230
Z85C30
44-Pin
92iLOE
Z8523008PSC/PEC
Z8523008VSC/VEC
Z8523010PSC
Z8523010VSC
Z8523010PEC
Z8523016VEC
Z8523016vsc
Z8523016PEC
Z8523008VSC
Z8523020PSC
z85230
z08030
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PDF
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marking wr6
Abstract: No abstract text available
Text: U s e r 's M a n u a l ^ S iL G E C hapter 5 R e g is t e r D e s c r ip t io n s 5.1 INTRODUCTION This section describes the function of the various bits in the registers of the device. Throughout this section the follow ing conventions will be used: Control bits may be written and read by the CPU and will
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DD37127
marking wr6
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Untitled
Abstract: No abstract text available
Text: PRELIMINARY PRODUCT SPECIFICATION < £ Z iIi3 G Z80181 Z181 SAC S mart A c c e s s C ontroller FEATURES • Z80180CompatibleMPUCore with 1 channel of Z85C30 SCC, Z80 CTC, two 8-bit general purpose parallel ports, and two chip select signals. ■ High speed operation 10/12.5 MHz
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Z80181
Z80180CompatibleMPUCore
Z85C30
16-bit
Z84C30
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Untitled
Abstract: No abstract text available
Text: P ro du c t S pecificat io n < £ Z iIß ö Z80C30/Z85C30 CMOS Z-BUS SCC S e r ia l C o m m u n ic a t io n C o n t r o l l e r FEATURES • Low power CMOS ■ Pin compatible fo NMOS versions ■ Two independent, 0 to 4.1 Mbit/second, full-duplex channels, each with a separate crystal oscillator, baud
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Z80C30/Z85C30
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PDF
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Untitled
Abstract: No abstract text available
Text: »2 JLC E PRELIMINARY PRODUCT SPECIFICATION Z 80185/ Z 80 1 95 SMART PERIPHERAL CONTROLLERS FEATURES • Z80185: 32 Kbytes ROM Z80195: ROMIess ■ Enhanced Z8S180 MPU - Code Compatible with Zilog's Z80 /Z180w CPUs - Extended Instructions - Two Enhanced DMA Channels
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Z80185:
Z80195:
Z8S180
/Z180w
16-Bit
P1284)
Z80185/ZS0195
Z80185
Z8018520FSC
33MHz
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SM TX 433
Abstract: SYNC12 CRC16
Text: < 2 > 2 iL 0 E PRELIMINARY PRODUCT SPECIFICATION Z80181 ZIO C o n t r o l le r ZILOG I/O C o n t r o lle r FEATURES • Z 8 0 180 C om patible MPU Core with 1 channel of Z85C30 SCC, Z80 CTC, two 8-bit general purpose parallel ports, and two chip select signals.
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Z80181
Z85C30
100-pin
SM TX 433
SYNC12
CRC16
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