SYM 111H Search Results

Contextual Info: REVISIONS APPROVED SYM DISCRETION DATE APPROVED 01/JU N /05’ A CONNIE A ‘ ‘ CUSTOMER DRAWING FOR REFERANCE ONLY, SAMPLES APPROVAL ARE REQUIRED!! V1.1 I PAGE 1 / 5 I NOTE: THIS DEVICE IS ROHS COMPLIANT. SYM A A DISCRETION NOTE ROHS STANDARD DATE 139.45

Contextual Info: PRELIMINARY I^ IIC R O N 2 M EG DRAM Il Jl X MT9LD272 X 72 DRAM M ODULE 2 MEG x 72 r \ I 11 C 16 MEGABYTE, ECC, 3.3V, FAST PAGE OR EDO PAGE MODE IV IU U U L t FEATURES PIN ASSIGNMENT (Front View) • JEDEC-standard ECC pinout in a 168-pin, dual-in-line memory module (DIMM)

HS253

Contextual Info: ADE-206-001 C H Feb. 1990 HG 62 E SERIES (H itachi C M O S Gate Array) 0 H IT A C H I The HG62E series is a master slice CMOS gate array o f w hich the gate length is 1 fim and uses 2-layer metal interconnect technology. Auto-diagnosis is a typical feature o f HG62E

Contextual Info: œ HARRIS S E M I C O N D U C T O R H S P 4 3 1 6 8 Dual FIR Filter December 1996 Features Description • Two Independent 8-Tap FIR Filters Configurable as a Single 16-Tap FIR The HSP43168 Dual FIR Filter consists of two independent 8-tap FIR filters. Each filter supports decimation from 1 to 16

HS173

Abstract: KCC CL-30 HG62E11 HS153 TTL 74 series HS135 HS153 sn j hs-135 HG62E33 HG62E08
Contextual Info: A D E - 2 0 6 - 0 0 1 C H Feb. 1 9 9 0 HG62E SERIES (H itachi C M O S Gate A rray) H IT A C H I The HG 62E series is a master slice CMOS gate array o f w h ich the gate length is 1 fim and uses 2-layer metal interconnect technology. Auto-diagnosis is a typ ica l feature o f HG 62E

HG62F

Abstract: V/HG62F HG62F43
Contextual Info: #U 210 HG62F SERIES Hitachi CMOS Gate Array High I/O to Gate Ratio JANUARY, 1990 0 H IT A C H I The F series consists of 6 masterslices ranging from 2,178 to 10,076 available gates with high I/O pin counts ranging from 136 pins to 208 pins. The HG62F series is a mastersliced gate array fabricated on 1.0

Contextual Info: STI7232205D2I-XXVG 168-PIN DIMMS 32M X 72 Bit DRAM DIMM Optimized for ECC FEATURES GENERAL DESCRIPTION • The Simple Technology STI7232205D2l-xxVG is an 32M x 72 bit Dynamic RAM high density memory module The module consists of thirty-six 16M x 4 bit DRAMs in 32-pin TSOP

HA17012

Abstract: HA17012G Digital to analog converter HA17012 7082 B amplifier HA17012B HA17012C HA17012P 3999
Contextual Info: , n M i / u # 1 2-bit Multiplying Digital-to-Analog Converter H A 1 7 0 1 2 is a m o n o lith ic high speed m ultip lying D /A co n ­ verter w hich provides 12-bit resultion and cu rrent output. It is divided into tw o groups according to the accu racy o f

FO 103H

Abstract: 1C11Ae
Contextual Info: f f t H U S E M I C O N D U C T O R v A R R HSP43168 I S Dual FIR Filter January 1994 Features Description • Two Independent 6-Tap FIR Filters Configurable as a Single 16-Tap FIR The HSP43168 Dual FIR Filter consists of tw o Independent 8-tap FIR filters. Each filter supports decim ation from 1 to 16

Contextual Info: HSP43168 HARRIS S E M I C O N D U C T O R Dual FIR Filter December 1996 Features Description • Two Independent 8-Tap FIR Filters Configurable as a Single 16-Tap FIR The HSP43168 Dual FIR Filter consists of two independent 8-tap FIR filters. Each filter supports decimation from 1 to 16

3350c

Abstract: data flow diagrams 4009A Tf11T HSP43168
Contextual Info: H S P 43168 HARRIS Dual FIR Filter November 1991 F e a tu re s D e s c rip tio n • Two The H SP 43168 Dual FIR Filter consists o f tw o independent 8 -ta p FIR filters. Each filter supports decim ation from 1 to 16 and provides o n -b o a rd storage fo r 3 2 sets o f coefficients. The B lo ck Diagram shows

KS88-SERIES

Abstract: "Frequency Dividers" KS88C2064 SM6309
Contextual Info: KS88C2064 1 PRODUCT OVERVIEW PRODUCT OVERVIEW KS88-SERIES MICROCONTROLLERS Samsung’s KS88 series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. Important CPU features include:

DN74LS02

Abstract: MA161 dn74LS02 PIN
Contextual Info: LS T T L DN74LS Series DN 74LS02 DN74LS02 DN 74- l S 0 2, Quad 2-input P o s itiv e NOR Gates • Description D N 7 4 L S 0 2 contains four 2-input positive isolation N O R gate circuits. ■ Features • L o w pow er consum ption P d = 1 lm W ty p ica l

DW 5255 S2

Abstract: BUZ 95 TB820 S3C8-Series
Contextual Info: S3C820B 1 PRODUCT OVERVIEW PRODUCT OVERVIEW S3C-SERIES MICROCONTROLLERS Samsung’s S3C8-series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. Important CPU features include:

BC1211

Contextual Info: ZL50012 Flexible 512-ch Digital Switch Data Sheet Features July 2005 • 512 channel x 512 channel non-blocking switch at 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s operation • Rate conversion between the ST-BUS inputs and ST-BUS outputs • Per-stream ST-BUS input with data rate selection

MS-026

Abstract: ZL50012 TFPW0 sto8b
Contextual Info: ZL50012 Flexible 512-ch Digital Switch Data Sheet Features VDD STi0-15 S/P Converter FPi CKi Input Timing • • 160 Pin LQFP 144 Ball LBGA • • • • Per-channel message mode Per-channel pseudo random bit sequence PRBS pattern generation and bit error detection

DS5722

Contextual Info: ZL50012 Flexible 512-ch Digital Switch Data Sheet Features VDD STi0-15 S/P Converter FPi CKi Input Timing • • 160 Pin LQFP 144 Ball LBGA • • • • Per-channel message mode Per-channel pseudo random bit sequence PRBS pattern generation and bit error detection

MS-026

Abstract: ZL50012
Contextual Info: ZL50012 Flexible 512-ch Digital Switch Data Sheet Features July 2004 • 512 channel x 512 channel non-blocking switch at 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s operation • Rate conversion between the ST-BUS inputs and ST-BUS outputs • Per-stream ST-BUS input with data rate selection

MS-026

Abstract: ZL50012 philips e3 STO11 ci 116h 4094m
Contextual Info: ZL50012 Flexible 512-ch Digital Switch Data Sheet Features VDD STi0-15 S/P Converter FPi CKi Input Timing • • 160 Pin LQFP 144 Ball LBGA • • • • Per-channel message mode Per-channel pseudo random bit sequence PRBS pattern generation and bit error detection

ZL50012QCG1

Abstract: MS-026 ZL50012 STO10
Contextual Info: ZL50012 Flexible 512-ch Digital Switch Data Sheet Features • April 2006 512 channel x 512 channel non-blocking switch at 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s operation • Rate conversion between the ST-BUS inputs and ST-BUS outputs • Per-stream ST-BUS input with data rate selection

SM 1-12H

Abstract: 29057 29058 1008HA 16EH00
Contextual Info: ADVANCE INFORMATION SERIES 100 FLASH MEMORY MINIATURE CARD Ì F M 0 0 2 A , ÌF M 0 0 4 A • Low-Cost Linear Flash Card ■ Miniature Card Specification Compliant ■ Single Supply SmartVoltage Operation — 5V or 3.3V Read/Write ■ Fast Read Performance

Contextual Info: 93C95 ATM 25.6 MB Transceiver , _ , _ , _ and Data Recovery 1C Technology, Incorporated ADVANCED DATA August 1995 Features Description • Integrated A TM25 PMD Sublayer The 93C95 is a highly integrated analog interface 1C for

101ZZ

Abstract: m1s23 PDCR 900 TLCS-900 TMP94C241C TMP94C241CF M2S22 PDCR 940 MNS20 B5WR
Contextual Info: TOSHIBA TMP94C241C CMOS 32-bit Microcontroller TMP94C241CF 1. O u t lin e an d Device Characteristics TMP94C241C is high-speed advanced 32-bit micro-controller developed for controlling equipment which processes mass data. TMP94C241C is a micro-controller which has a high-performance CPU 900/H2 CPU and various

GR-1244-CORE

Abstract: MS-026 ZL50011
Contextual Info: ZL50011 Flexible 512-ch DX with on-chip DPLL Data Sheet Features VDD • • • Applications • • • • • Small and medium digital switching platforms Access Servers Time Division Multiplexers Computer Telephony Integration Digital Loop Carriers VSS