SY10H601JCTR Search Results

SY10H601JCTR Datasheets (4)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
SY10H601JCTR		Micrel Semiconductor	9 Bit ECL-to-TTL with 3-State Enable Translator		Original	PDF
SY10H601JCTR		Micrel Semiconductor	9-BIT ECL-TO-TTL WITH 3-STATE ENABLE		Original	PDF
SY10H601JC-TR		Microchip Technology	Integrated Circuits (ICs) - Logic - Translators, Level Shifters - IC TRNSLTR UNIDIRECTIONAL 28PLCC		Original	PDF
SY10H601JCTR		Synergy Semiconductor	9-BIT ECL-TO-TTL WITH 3-STATE ENABLE		Scan	PDF

SY10H601JCTR Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
Contextual Info: >0 » 9-BIT ECL-TO-TTL WITH 3-STATE ENABLE SYNERG Y SY10H601 SY100H601 SEMICONDUCTOR DESCRIPTION FEATURES 9-bit ideal for byte-parity applications 3-state TTL outputs Flow-through configuration Extra TTL and ECL power/ground pins to minimize switching noise	OCR Scan	SY10H601 SY100H601 200pF 10Hxxx) 100Hxxx) SY10/100H601 28-lead	PDF
Contextual Info: SY10H601 SY100H601 FINAL 9-BIT ECL-TO-TTL WITH 3-STATE ENABLE DESCRIPTION FEATURES OEECL OETTL 25 24 23 22 21 20 19 Q4 Q3 26 18 27 17 VCCT Q2 GND Q1 28 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 Q0 ECL D8 16 TOP VIEW PLCC 1 15 2 14 3 13 4 12 5 6 7 TTL 8 9 D8	Original	SY10H601 SY100H601 SY10H601JCTR J28-1 SY100H601JC SY100H601JCTR	PDF
SY100H601 Abstract: SY10H601 SY10H601JC Contextual Info: • ■ ■ ■ ■ ■ 9-bit ideal for byte-parity applications 3-state TTL outputs Flow-through configuration Extra TTL and ECL power/ground pins to minimize switching noise ECL and TTL 3-state control inputs 4.8ns max. delay into 50pF, 9.6ns into 200pF all	Original	SY100H601 SY10H601 200pF 10Hxxx) 100Hxxx) MC10H/100H601 28-pin SY10/100H601 SY100H601 SY10H601 SY10H601JC	PDF
SY100H601 Abstract: SY100H601JC SY10H601 SY10H601JC SY10H601JCTR Contextual Info: 9-BIT ECL-TO-TTL WITH 3-STATE ENABLE DESCRIPTION FEATURES OEECL OETTL 25 24 23 22 21 20 19 Q4 Q3 26 18 27 17 VCCT Q2 GND Q1 28 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 Q0 ECL D8 16 TOP VIEW PLCC 1 15 2 14 3 13 4 12 5 6 7 TTL 8 9 D8 D7 VCCE D6 D5 D4 D3 10 11	Original	SY10H601JCTR J28-1 SY100H601JC SY100H601JCTR SY10H601 SY100H601 J28-1) SY100H601 SY100H601JC SY10H601 SY10H601JC SY10H601JCTR	PDF
Contextual Info: >0» 9-BIT ECL-TO-TTL WITH 3-STATE ENABLE SYNERG Y SY10H601 SY100H601 SEMICONDUCTOR DESCRIPTION FEATURES 9-bit ideal for byte-parity applications 3-state TTL outputs Flow-through configuration Extra TTL and ECL power/ground pins to minimize switching noise	OCR Scan	SY10H601 SY100H601 200pF 10Hxxx) 100Hxxx) SY10/100H601 28-lead	PDF
Contextual Info: * 9-BIT ECL-TO-TTL WITH 3-STATE ENABLE SYNERGY SY10H601 SY100H601 SEMICONDUCTOR FEATURES DESCRIPTION • 9-bit ideal for byte-parity applications ■ 3-state TTL outputs ■ Flow-through configuration ■ Extra TTL and ECL power/ground pins to minimize switching noise	OCR Scan	SY10H601 SY100H601 200pF 10Hxxx) SY10/100H601 28-lead SY10H601JC J28-1	PDF
Contextual Info: <o> SY N E R G Y 9-BIT ECL TO-T n Sv i WI TH 3-STATE F N A B ! !: 'ncioHbOl S E M IC O N D U C T O R FEA TU R E S • ■ ■ ■ 9-bit ideal for byte-parity applications 3-state TTL outputs Flow-through configuration Extra TTL and ECL power/ground pins to minimize	OCR Scan	SY10/100H601 28-lead 200pF 200pF SY10H601JC	PDF
SY100H601 Abstract: SY10H601 SY10H601JC Contextual Info: « c y A /C D /^ v 9 -B IT E C L -T O -T T L s E lc O N M C T C M SY10H601 W IT H 3 ' S T A T E E N A B L E FEATURES SY100H601 DESCRIPTION I 9-bit ideal for byte-parity applications 3-state TTL outputs T he SY10/100H601 are 9-bit, dual supply ECL-to-TTL translators. Devices in the S ynergy 9-bit tran sla to r series	OCR Scan	200pF MC10H/100H601 SY10/100H601 28-lead 200pF SY100H601 SY10H601 SY10H601JC	PDF
SY100H601 Abstract: SY100H601JC SY10H601 SY10H601JC SY10H601JCTR Contextual Info: SYNERGY 9-BIT ECL-TO-TTL WITH 3-STATE ENABLE SEMICONDUCTOR SYNERGY SY10H601 SY100H601 SY10H601 SY100H601 SEMICONDUCTOR DESCRIPTION FEATURES • 9-bit ideal for byte-parity applications ■ 3-state TTL outputs ■ Flow-through configuration ■ Extra TTL and ECL power/ground pins to minimize	Original	SY10H601 SY100H601 200pF 10Hxxx) 100Hxxx) SY10/100H601 28-lead SY100H601 SY100H601JC SY10H601 SY10H601JC SY10H601JCTR	PDF
Contextual Info: * SYNERG Y 9-BIT ECL-TO-TTL WITH 3-STATE ENABLE SY10H601 SY100H601 SEMICONDUCTOR DESCRIPTION FEATURES 9-bit ideal for byte-parity applications 3-state TTL outputs Flow-through configuration Extra TTL and ECL power/ground pins to minimize switching noise ECL and TTL 3-state control inputs	OCR Scan	SY10H601 SY100H601 200pF 10Hxxx) 100Hxxx) MC10H/100H601 28-pin SY10/100H601 28-lead	PDF