SY100S336ADC Search Results

Contextual Info: ENHANCED 4-STAGE COUNTER/SHIFT REGISTER SYNERG Y SY100S336A SEMICONDUCTOR FEATURES DESCRIPTION Max. shift frequency of 700MHz Clock to Q delay max. of 1100ps Sn to TC speed improved by 50% Sn set-up and hold time reduced by more than 50% Iee min. of -170m A

Contextual Info: O • ira ENHANCED 4-STAGE COUNTER/SHIFT REGISTER ^ SYNERGY cvm n^A oYi 00S336A SEMICONDUCTOR FEATURES DESCRIPTION ■ Max. shift frequency of 700MHz ■ Clock to Q delay max. of 110Ops ■ Sn to TC speed improved by 50% ■ Sn set-up and hold tim e reduced by more than 50%

F100K

Abstract: SY100S336 SY100S336A SY100S336ADC
Contextual Info: ENHANCED 4-STAGE COUNTER/SHIFT REGISTER m v SYNERGY . Vim <N «4 S i i 00S336A S E M IC O N D U C T O R DESCRIPTION FEATURES • Max. shift frequency of 700MHz ■ Clock to Q delay max. of 110Ops ■ Sn to TC speed improved by 50% ■ Sn set-up and hold time reduced by more than 50%

Contextual Info: * 4-STAGE COUNTER/ SHIFT REGISTER SYNERGY SY100S336A SEMICONDUCTOR FEATU R ES DESCRIPTION • Max. shift frequency of 700MHz ■ Clock to Q delay max. of 1lOOps ■ Sn to TC speed improved by 50% ■ Sn set-up and hold time reduced by more than 50% ■ I e e min. of -170mA

F100K

Abstract: SY100S336 SY100S336A SY100S336ADC PN800
Contextual Info: 4-STAGE COUNTER/ SHIFT REGISTER SYNERGY S EM IC O N D U C TO R FEATURES I l I l l I SY100S336A D E S C R IP T IO N Max. shift frequency of 700MHz Clock to Q delay max. of HOOps Sn to TC speed Improved by 50% Sn set-up and hold time reduced by more than 50%