Untitled
Abstract: No abstract text available
Text: M470L6423DN0 200pin DDR SDRAM SODIMM 512MB DDR SDRAM MODULE 64Mx64 based on sTSOP 32Mx8 DDR SDRAM 200pin SODIMM 64bit Non-ECC/Parity Revision 0.0 May 2002 Rev. 0.0 May 2002 M470L6423DN0 200pin DDR SDRAM SODIMM Revision History Revision 0.0 (May 2002) - First release.
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M470L6423DN0
200pin
512MB
64Mx64
32Mx8
64bit
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K4S280832CNL
Abstract: No abstract text available
Text: shrink-TSOP K4S280832C-N CMOS SDRAM 4M x 8Bit x 4 Banks Synchronous DRAM in sTSOP FEATURES GENERAL DESCRIPTION • JEDEC standard 3.3V power supply The K4S280832C-N is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 4,194,304 words by 8
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K4S280832C-N
K4S280832C-N
54-sTSOP
K4S280832CNL
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BS62LV256-70
Abstract: M5M5408 BS62UV256-15 M5M5408B-55 t0808
Text: Package Descriptions PC / PI = PDIP SRAM CROSS REFERENCE 7700 Irvine Center Dr. STE: 420 SC / SI = SOP Irvine, CA 92618 Contact: TC / TI = TSOP Lena Patel STC / STI = STSOP BC / BI = BGA 8 x 10 email: lena@brilliancesemi.com Phone Number: 949-789-6274 Fax Number: 949-789-6277
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32Kx8
128Kx8
256Kx8
BS62XV256-25
BS62UV256-15
BS62LV256-70
BS62XV1024-25
BS62UV1024-15
BS62LV1024-70
BS62XV2000-25
BS62LV256-70
M5M5408
BS62UV256-15
M5M5408B-55
t0808
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ly62l256
Abstract: No abstract text available
Text: LY62L256 32K X 8 BIT LOW POWER CMOS SRAM Rev. 1.3 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Description Initial Issue Revised STSOP Package Outline Dimension Deleted L Spec. Revised VTERM to VT1 and VT2 Revised Test Condition of ISB1/IDR
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LY62L256
28-pin
ly62l256
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Untitled
Abstract: No abstract text available
Text: HY62U8100B Series 128Kx8bit CMOS SRAM Document Title 128K x8 bit 3.0V Low Power CMOS slow SRAM Revision History Revision No History Draft Date Remark 10 Initial Revision History Insert Revised - Insert 70ns Part Jul.25.2000 Final 11 Change the Notch Location of sTSOP
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HY62U8100B
128Kx8bit
HY62U8100B
100ns
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64Mb samsung SDRAM
Abstract: DDR333 DDR266
Text: DDR SDRAM 256Mb E-die x4, x8 DDR SDRAM 256Mb E-die DDR SDRAM Specification 54pin sTSOP(II) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
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256Mb
54pin
64Mb samsung SDRAM
DDR333
DDR266
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Untitled
Abstract: No abstract text available
Text: 512MB Unbuffered SODIMM based on sTSOP Pb-Free DDR SDRAM DDR SDRAM Unbuffered SODIMM 200pin Unbuffered SODIMM based on 256Mb E-die (x8) with 64-bit Non ECC 54 sTSOP(II) with Pb-Free (RoHS compliant) Revision 1.1 Oct. 2004 Revision 1.1 Oct. 2004 512MB Unbuffered SODIMM(based on sTSOP) Pb-Free
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512MB
200pin
256Mb
64-bit
M470L6423EV0-C
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Untitled
Abstract: No abstract text available
Text: DDR SDRAM 512Mb B-die x8 DDR SDRAM 512Mb B-die DDR400 SDRAM Specification sTSOP(II) (400mil x 441mil) Revision 1.1 Rev. 1.1 November 2004 DDR SDRAM 512Mb B-die (x8) DDR SDRAM 512Mb B-die Revision History Revision 1.0 (October, 2003) - First release Revision 1.1 (November, 2004)
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512Mb
DDR400
400mil
441mil)
200MHz
400Mbps
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Untitled
Abstract: No abstract text available
Text: K6F2008V2M, K6F2008S2M, K6F2008R2M Family CMOS SRAM Document Title 256Kx8 bit Super Low Power and Low Voltage Full CMOS Static RAM Revision History Revision No. History Draft Date Remark 0.0 Initial draft October 2, 1996 Advance 0.1 Revise - Remove sTSOP1 from product
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K6F2008V2M,
K6F2008S2M,
K6F2008R2M
256Kx8
KM68F2000
100ns)
0820F)
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Untitled
Abstract: No abstract text available
Text: DDR SDRAM 512Mb B-die x4, x8 DDR SDRAM 512Mb B-die DDR SDRAM Specification sTSOP(II) (400mil x 441mil) Revision 1.2 October, 2004 Rev. 1.2 October, 2004 DDR SDRAM 512Mb B-die (x4, x8) DDR SDRAM 512Mb B-die Revision History Revision 0.0 (February, 2003) - First version for internal review
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512Mb
400mil
441mil)
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M470L6524FL0
Abstract: M470L2923F60
Text: 512MB, 1GB Unbuffered SODIMM DDR SDRAM DDR SDRAM Unbuffered SODIMM 200pin Unbuffered SODIMM based on 512Mb F-die 66 TSOP-II & 54 sTSOP-II with Lead-Free and Halogen-Free RoHS compliant INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
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512MB,
200pin
512Mb
64Mx8
sTSOPII-300mil
K4H510838F-6*
M470L6524FL0
M470L2923F60
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Untitled
Abstract: No abstract text available
Text: 256MB, 512MB, 1GB Unbuffered SODIMM DDR SDRAM DDR SDRAM Unbuffered Module 184pin Unbuffered Module based on 512Mb D-die 66 TSOP-II & 54 sTSOP-II with Pb-Free RoHS compliant INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
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256MB,
512MB,
184pin
512Mb
64Mx8
sTSOPII-300mil
K4H510838D-V*
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Untitled
Abstract: No abstract text available
Text: DDR SDRAM 256MB, 512MB, 1GB Unbuffered SODIMM Pb-Free DDR SDRAM SODIMM 200pin Unbuffered SODIMM based on 512Mb B-die with 64 / 72-bit Non ECC / ECC 66 TSOP(II)/54 sTSOP(II) with Pb-Free (RoHS compliant) Revision 1.2 Oct. 2004 Revision 1.2 Oct. 2004 256MB, 512MB, 1GB Unbuffered SODIMM Pb-Free
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256MB,
512MB,
200pin
512Mb
72-bit
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Untitled
Abstract: No abstract text available
Text: Preliminary DDR SDRAM DDR SDRAM 512Mb D-die x8 512Mb D-die DDR SDRAM Specification 54 sTSOP-II with Pb-Free (400mil x 441mil) (RoHS compliant) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
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512Mb
400mil
441mil)
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Untitled
Abstract: No abstract text available
Text: LY62W256 32K X 8 BIT LOW POWER CMOS SRAM Rev. 1.2 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Description Initial Issue Merge 2.7~3.6V and 4.5~5.5V to 2.7~5.5V Revised STSOP Package Outline Dimension Lyontek Inc. reserves the rights to change the specifications and products without notice.
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LY62W256
LY62W256
144-bit
28-pin
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Untitled
Abstract: No abstract text available
Text: LY61256 32K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.3 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Description Initial Issue Delete Icc1/ ISB Spec. Adding Skinny P-DIP Revised STSOP Package Outline Dimension Lyontek Inc. reserves the rights to change the specifications and products without notice.
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LY61256
LY61256
144-bit
28-pin
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K4H511638D
Abstract: M470L3324DU0
Text: 256MB, 512MB, 1GB Unbuffered SODIMM Preliminary DDR SDRAM DDR SDRAM Unbuffered Module 184pin Unbuffered Module based on 512Mb D-die 66 TSOP-II & 54 sTSOP-II with Pb-Free RoHS compliant INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
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256MB,
512MB,
184pin
512Mb
64Mx8
sTSOPII-300mil
K4H510838D-V*
K4H511638D
M470L3324DU0
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K4S561632J
Abstract: m464s64* samsung K4S560832J
Text: 256MB, 512MB Unbuffered SODIMM SDRAM SDRAM Unbuffered SODIMM 144pin Unbuffered SODIMM based on 256Mb J-die 54 TSOP-II/sTSOP II with Lead-Free and Halogen-Free RoHS compliant INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE
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256MB,
512MB
144pin
256Mb
32Mx8
K4S560832J
K4S561632J
m464s64* samsung
K4S560832J
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DSASW0034363
Abstract: DDR266 DDR333 DDR400 DDR500
Text: DDR SDRAM Code Information 1/2 Last Updated : August 2009 K4HXXXXXXX - XXXXXXX 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1. Memory (K) 11. "─" 2. DRAM : 4 12. Package T : TSOP2 U : TSOP2 (Lead Free) L : TSOP2 (Lead-Free & Halogen-Free) N : sTSOP2 V : sTSOP2 (Lead Free)
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64Mb/128Mb
4K/64ms
128Mb,
512Mb,
8K/64ms
256Mb,
DSASW0034363
DDR266
DDR333
DDR400
DDR500
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k4s-x
Abstract: No abstract text available
Text: Sync DRAM Code Information 1/2 Last Updated : August 2009 K4SXXXXXXX - XXXXXXX 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1. Memory (K) 10. Generation 2. DRAM : 4 11. “—” 3. Small Classification S : SDRAM 12. Package N : STSOP2 T : TSOP2 U : TSOP2 (Lead-Free)
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2K/32ms
4K/64ms
8K/64ms
256Mb
J-die/128Mb
PC133
k4s-x
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DDR400
Abstract: K4H511638B M470L3324BT
Text: 256MB, 512MB, 1GB Unbuffered SODIMM DDR SDRAM DDR SDRAM Unbuffered Module 184pin Unbuffered Module based on 512Mb B-die 66 TSOP-II & 54 sTSOP-II INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
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256MB,
512MB,
184pin
512Mb
64Mx8
sTSOPII-300mil
K4H510838B
DDR400
K4H511638B
M470L3324BT
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Ablestik
Abstract: cel-9200u ablestik 84-1LMISR4 140C JESD22 Hitachi CEL
Text: Cypress Semiconductor Qualification Report QTP# 97213, Version 1.0 February, 1998 32 Ld STSOP Package OSE, Taiwan Assembly Cypress Semiconductor Assembly: OSE, Taiwan Package: 32 Ld STSOP QTP# 97213, V. 1.0 2 of 4 February, 1998 PLASTIC PACKAGE/ASSEMBLY DESCRIPTION
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9200U
84-1LMISR4
JESD22-A112
30C/60
CY7C1512-ZAC
Ablestik
cel-9200u
ablestik 84-1LMISR4
140C
JESD22
Hitachi CEL
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K4S281632B-N
Abstract: No abstract text available
Text: shrink-TSOP CMOS SDRAM K4S281632B-N 2M x 16Bit x 4 Banks Synchronous DRAM in sTSOP FEATURES GENERAL DESCRIPTION • JEDEC standard 3.3V power supply The K4S281632B-N is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by
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K4S281632B-N
16Bit
K4S281632B-N
54-sTSOP
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Untitled
Abstract: No abstract text available
Text: CMOS 1M 128K x 8 Static Ram FEATURES • Access time: 85 ns (MAX.), 100 ns (MAX.) • Current consumption: Operating: 40 mA (MAX.) 6 mA (MAX.) (tRc, twc = 1 M-s) Standby: 45 (MAX.) PIN CONNECTIONS 32-PIN TSOP 32-PIN STSOP / A „ C 1• Ag L 2 Ag C 3 *13 □ 4
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32-pin
LH52D1000
LH52D1000
32-pin,
TSOP32-P-0820)
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