AN1525
Abstract: ST24C04
Text: AN1525 APPLICATION NOTE I2C Communication between ST52x520 and EEPROM Author: C.Ruggieri 1 INTRODUCTION This AN shows an example of how to interface style I2C EEPROM with an ST52x520 microcontroller using an I2C protocol. An ST24C04 4Kbit memory is used for this example, although similar thoughts are also
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AN1525
ST52x520
ST24C04
AN1525
ST24C04
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PDIP28
Abstract: ST52T521 22 CDIP T521
Text: ST52T520/E520/T521 ST52T520/E520/T521 8-BIT INTELLIGENT CONTROLLER UNIT ICU Two Timer/PWMs, ADC, I2C, SPI PRELIMINARY DATASHEET Memories • Up to 8 Kbytes EPROM/OTP ■ Up to 512 bytes of RAM ■ Readout protection Core ■ Register File based architecture
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ST52T520/E520/T521
16ronics.
PDIP28
ST52T521
22 CDIP
T521
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FUZZY MICROCONTROLLER ALGORITHM
Abstract: No abstract text available
Text: ST52F510/F513/F514 ST52F510/F513/F514 8-BIT INTELLIGENT CONTROLLER UNIT ICU Two Timer/PWMs, ADC, I2C, SPI, SCI TARGET SPECIFICATION Memories • Up to 8 Kbytes Single Voltage Flash Memory ■ Up to 512 bytes of RAM ■ Up to 4 Kbytes Data EEPROM ■
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ST52F510/F513/F514
10-bit
FUZZY MICROCONTROLLER ALGORITHM
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Untitled
Abstract: No abstract text available
Text: ST52T520/E520/T521 ST52T520/E520/T521 8-BIT INTELLIGENT CONTROLLER UNIT ICU Two Timer/PWMs, ADC, I2C, SPI PRELIMINARY DATASHEET Memories • Up to 8 Kbytes EPROM/OTP ■ Up to 512 bytes of RAM ■ Readout protection Core ■ Register File based architecture
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ST52T520/E520/T521
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pbi07
Abstract: F504 PDIP28 ST52F500
Text: ST52F500/F503/F504 ST52F500/F503/F504 8-BIT INTELLIGENT CONTROLLER UNIT ICU Two Timer/PWMs, I2C, SPI TARGET SPECIFICATION Memories • Up to 8 Kbytes Single Voltage Flash Memory ■ Up to 512 bytes of RAM ■ Up to 4 Kbytes Data EEPROM ■ In Situ Programming in Flash devices (ISP)
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ST52F500/F503/F504
pbi07
F504
PDIP28
ST52F500
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Untitled
Abstract: No abstract text available
Text: ST52T520/E520/T521 ST52T520/E520/T521 8-BIT INTELLIGENT CONTROLLER UNIT ICU Two Timer/PWMs, ADC, I2C, SPI PRELIMINARY DATASHEET Memories • Up to 8 Kbytes EPROM/OTP ■ Up to 512 bytes of RAM ■ Readout protection Core ■ Register File based architecture
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ST52T520/E520/T521
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PI fuzzy
Abstract: No abstract text available
Text: ST FIVE 508 series ST FIVE 508 series 8-BIT INTELLIGENT CONTROLLER UNIT ICU FAMILY Timer/PWMs, ADC, SCI, I2C, SPI TARGET SPECIFICATION Memories • Up to 8 Kbytes EPROM/OTP or Single Voltage Flash. Up to 64 Kbytes of Program/Data Memory addressing capability
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Untitled
Abstract: No abstract text available
Text: ST52F500/F503/F504 ST52F500/F503/F504 8-BIT INTELLIGENT CONTROLLER UNIT ICU Two Timer/PWMs, I2C, SPI TARGET SPECIFICATION Memories • Up to 8 Kbytes Single Voltage Flash Memory ■ Up to 512 bytes of RAM ■ Up to 4 Kbytes Data EEPROM ■ In Situ Programming in Flash devices (ISP)
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ST52F500/F503/F504
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locking eprom
Abstract: e520
Text: ST52T520/E520/T521 ST52T520/E520/T521 8-BIT INTELLIGENT CONTROLLER UNIT ICU Two Timer/PWMs, ADC, I2C, SPI PRELIMINARY DATASHEET Memories • Up to 8 Kbytes EPROM/OTP ■ Up to 512 bytes of RAM ■ Readout protection Core ■ Register File based architecture
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ST52T520/E520/T521
locking eprom
e520
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t52111
Abstract: No abstract text available
Text: ST52T520/E520/T521 ST52T520/E520/T521 8-BIT INTELLIGENT CONTROLLER UNIT ICU Two Timer/PWMs, ADC, I2C, SPI PRELIMINARY DATASHEET Memories • Up to 8 Kbytes EPROM/OTP ■ Up to 512 bytes of RAM ■ Readout protection Core ■ Register File based architecture
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ST52T520/E520/T521
t52111
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E520
Abstract: No abstract text available
Text: ST52T520/E520 8-BIT INTELLIGENT CONTROLLER UNIT ICU Two Timer/PWMs, ADC, I2C, SPI TARGET SPECIFICATION Memories • Up to 8 Kbytes EPROM/OTP ■ Up to 512 bytes of RAM ■ Readout protection Core Register File based architecture ■ ■ 105 basic instructions
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ST52T520/E520
E520
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triac tag 9131
Abstract: ST52 CH2017 TRIAC TAG 265 600 tag triac codes 20 to 99
Text: VISUAL FIVE 5.0 USER MANUAL PRELIMINARY DATA Rev. 2.5 - September 2002 VISUAL FIVE 5.0 OWNERSHIP STMicroelectronics is the sole owner of the Software contained in the package. STMicroelectronics is the holder of the copyright to the Software, including without limitation such aspects
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Untitled
Abstract: No abstract text available
Text: ST52T520/E520/T521 ST52T520/E520/T521 8-BIT INTELLIGENT CONTROLLER UNIT ICU Two Timer/PWMs, ADC, I2C, SPI PRELIMINARY DATASHEET Memories • Up to 8 Kbytes EPROM/OTP ■ Up to 512 bytes of RAM ■ Readout protection Core ■ Register File based architecture
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