SN74LVC10 Search Results

Contextual Info: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE SCAS284K – JANUARY 1993 – REVISED SEPTEMBER 2002 D 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3C 3B 3A 3Y RGY PACKAGE TOP VIEW description/ordering information This triple 3-input positive-NAND gate is designed

Contextual Info: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCAS284O – JANUARY 1993 – REVISED JULY 2005 FEATURES • 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3C 3B 3A 3Y RGY PACKAGE TOP VIEW 1B 2A 2B 2C 2Y VCC • 1 1 14 13 1C 12 1Y 2 3 4 11 3C 5 6 10 3B

Contextual Info: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCAS284O – JANUARY 1993 – REVISED JULY 2005 FEATURES • 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3C 3B 3A 3Y RGY PACKAGE TOP VIEW 1B 2A 2B 2C 2Y VCC • 1 1 14 13 1C 12 1Y 2 3 4 11 3C 5 6 10 3B

Contextual Info: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCAS284O – JANUARY 1993 – REVISED JULY 2005 FEATURES • 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3C 3B 3A 3Y RGY PACKAGE TOP VIEW 1B 2A 2B 2C 2Y VCC • 1 1 14 13 1C 12 1Y 2 3 4 11 3C 5 6 10 3B

SN74LVC10

Contextual Info: SN74LVC10 TRIPLE 3-INPUT POSITIVE-NAND GATE JA N U A R Y 1993 D, DB, OR PW PACKAGE TOP VIEW 1A [ EPIC (Enhanced-Performance Implanted CMOS) Submicron Process • Designed to Facilitate Incident Wave Switching for Line Impedances of 50 Q or Greater •

SN74LVC10A

Contextual Info: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE S C A S284D - JA N U A R Y 1993 - R EVISED JA N U A R Y 1997 EPIC Enhanced-Performance Implanted D, DB, O R PW PACKAGE (TOP VIEW CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V

122B4

Abstract: SN74LVC10A
Contextual Info: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE SC A S 284F - JA N U A R Y 1993 - R EVISED JU NE 1998 • • • • • • • EPIC Enhanced-Performance Implanted D, DB, O R PW PACKAGE (TOP VIEW CMOS) Submicron Process ESD Protection Exceeds 2000 V Per

SN74LVC10A

Contextual Info: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE SCAS284G – JANUARY 1993 – REVISED OCTOBER 1998 D D D D D D D EPIC  Enhanced-Performance Implanted CMOS Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)

Contextual Info: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE SCAS284E - JANUARY 1993 - REVISED JANUARY 1998 • EPIC Enhanced-Performance Implanted CMOS Submicron Process • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)

Contextual Info: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE SCAS284J – JANUARY 1993 – REVISED AUGUST 2002 D 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3C 3B 3A 3Y RGY PACKAGE TOP VIEW description/ordering information This triple 3-input positive-NAND gate is designed

Contextual Info: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE SCAS284H – JANUARY 1993 – REVISED MARCH 2002 D D D D D D, DB, NS, OR PW PACKAGE TOP VIEW Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C

Contextual Info: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCAS284O – JANUARY 1993 – REVISED JULY 2005 FEATURES • 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3C 3B 3A 3Y RGY PACKAGE TOP VIEW 1B 2A 2B 2C 2Y VCC • 1 1 14 13 1C 12 1Y 2 3 4 11 3C 5 6 10 3B

Contextual Info: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE SCAS284I – JANUARY 1993 – REVISED JULY 2002 D D D D D D D D, DB, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 4.9 ns Typical VOLP (Output Ground Bounce)

Contextual Info: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCAS284O – JANUARY 1993 – REVISED JULY 2005 FEATURES • 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3C 3B 3A 3Y RGY PACKAGE TOP VIEW 1B 2A 2B 2C 2Y VCC • 1 1 14 13 1C 12 1Y 2 3 4 11 3C 5 6 10 3B

Contextual Info: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCAS284O – JANUARY 1993 – REVISED JULY 2005 FEATURES • 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3C 3B 3A 3Y RGY PACKAGE TOP VIEW 1B 2A 2B 2C 2Y VCC • 1 1 14 13 1C 12 1Y 2 3 4 11 3C 5 6 10 3B

Contextual Info: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCAS284O – JANUARY 1993 – REVISED JULY 2005 FEATURES • 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3C 3B 3A 3Y RGY PACKAGE TOP VIEW 1B 2A 2B 2C 2Y VCC • 1 1 14 13 1C 12 1Y 2 3 4 11 3C 5 6 10 3B

A115-A

Abstract: SN74LVC10A SN74LVC10AD SN74LVC10ADR SN74LVC10ARGYR
Contextual Info: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCAS284O – JANUARY 1993 – REVISED JULY 2005 FEATURES • 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3C 3B 3A 3Y RGY PACKAGE TOP VIEW 1B 2A 2B 2C 2Y VCC • 1 1 14 13 1C 12 1Y 2 3 4 11 3C 5 6 10 3B

Contextual Info: SN74LVC10 TRIPLE 3-INPUT POSITIVE-NAND GATE SCAS284 - JANUARY 1993 - REVISED MARCH 1994 EPIC Enhanced-Performance Implanted CMOS Submicron Process D, DB, OR PW PACKAGE (TOP VIEW) Typical V q l p (Output Ground Bounce) < 0.8 V at Vc c = 3.3 V, TA = 25°C

A115-A

Abstract: SN74LVC10A SN74LVC10AD SN74LVC10ADR SN74LVC10ARGYR
Contextual Info: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCAS284O – JANUARY 1993 – REVISED JULY 2005 FEATURES • 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3C 3B 3A 3Y RGY PACKAGE TOP VIEW 1B 2A 2B 2C 2Y VCC • 1 1 14 13 1C 12 1Y 2 3 4 11 3C 5 6 10 3B

Contextual Info: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE SCAS284K – JANUARY 1993 – REVISED SEPTEMBER 2002 D 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3C 3B 3A 3Y RGY PACKAGE TOP VIEW description/ordering information This triple 3-input positive-NAND gate is designed

SN74LVC10A

Contextual Info: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE S C AS 284E - JA N U A R Y 1993 - R EVISED JA N U A R Y 1998 EPIC Enhanced-Performance Implanted D, DB, O R PW PACKAGE (TOP VIEW CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V

A115-A

Abstract: SN74LVC10A SN74LVC10AD SN74LVC10ADR SN74LVC10ARGYR
Contextual Info: SN74LVC10A TRIPLE 3ĆINPUT POSITIVEĆNAND GATE SCAS284M − JANUARY 1993 − REVISED JULY 2003 D 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3C 3B 3A 3Y RGY PACKAGE TOP VIEW description/ordering information This triple 3-input positive-NAND gate is designed

Contextual Info: SN74LVC10 TRIPLE 3-INPUT POSITIVE-NAND GATE S C A S 2 8 4 -JANUARY 1 9 9 3 -R E V IS E D MARCH 1994 D, DB, OR PW PACKAGE TOP VIEW EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Typical V q l p (Output Ground Bounce) < 0.8 V at Vc c = 3.3 V, TA = 25°C

LC10A

Contextual Info: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCAS284O – JANUARY 1993 – REVISED JULY 2005 FEATURES • 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3C 3B 3A 3Y RGY PACKAGE TOP VIEW 1B 2A 2B 2C 2Y VCC • 1 1 14 13 1C 12 1Y 2 3 4 11 3C 5 6 10 3B