SN74LVC08 Search Results

A115-A

Abstract: C101 SN54LVC08A SN74LVC08A LC08A top marking LC08A
Contextual Info: SN54LVC08A, SN74LVC08A www.ti.com SCAS283Q – JANUARY 1993 – REVISED OCTOBER 2010 QUADRUPLE 2-INPUT POSITIVE-AND GATES Check for Samples: SN54LVC08A, SN74LVC08A FEATURES 1 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 1B 1Y 2A 2B 2Y 14 1B 1A NC

Contextual Info: SN74LVC08A-EP QUADRUPLE 2-INPUT POSITIVE-AND GATE www.ti.com SCAS731D – NOVEMBER 2003 – REVISED SEPTEMBER 2007 • FEATURES 1 • • • • • Controlled Baseline – One Assembly – One Test Site – One Fabrication Site Extended Temperature Performance of –40°C

Contextual Info: SN74LVC08A-Q1 QUADRUPLE 2-INPUT POSITIVE-AND GATE SCES480C − AUGUST 2003 − REVISED JANUARY 2008 D Qualified for Automotive Applications D ESD Protection Exceeds 2000 V Per D D D D D D OR PW PACKAGE TOP VIEW MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)

Contextual Info: SN54LVC08A, SN74LVC08A www.ti.com SCAS283Q – JANUARY 1993 – REVISED OCTOBER 2010 QUADRUPLE 2-INPUT POSITIVE-AND GATES Check for Samples: SN54LVC08A, SN74LVC08A FEATURES 1 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 1B 1Y 2A 2B 2Y 14 1B 1A NC

Contextual Info: SN54LVC08A, SN74LVC08A QUADRUPLE 2-INPUT POSITIVE-AND GATES SCAS283G – JANUARY 1993 – REVISED JUNE 1998 D D D D D D EPIC  Enhanced-Performance Implanted CMOS Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V

LC08A marking

Abstract: LC08A top marking lc08a
Contextual Info: SN54LVC08A, SN74LVC08A QUADRUPLE 2-INPUT POSITIVE-AND GATES SCAS283J – JANUARY 1993 – REVISED AUGUST 2002 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 1B 1Y 2A 2B 2Y 14 1B 1A NC VCC 4B 1 13 4B 2 12 4A 3 4 11 4Y GND 10 3B 9 3A 5 6 7 8 SN54LVC08A . . . FK PACKAGE

Contextual Info: SN54LVC08A, SN74LVC08A QUADRUPLE 2-INPUT POSITIVE-AND GATES SCAS283H – JANUARY 1993 – REVISED MARCH 2002 D D D D D SN54LVC08A . . . J OR W PACKAGE SN74LVC08A . . . D, DB, NS, OR PW PACKAGE TOP VIEW Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C

Contextual Info: SN74LVC08AĆQ1 QUADRUPLE 2ĆINPUT POSITIVEĆAND GATE SCES480B − AUGUST 2003 − REVISED MAY 2004 D Qualification in Accordance With D D D D D D D Typical VOLP Output Ground Bounce AEC-Q100† Qualified for Automotive Applications Customer-Specific Configuration Control

Contextual Info: SN74LVC08A-EP QUADRUPLE 2-INPUT POSITIVE-AND GATE www.ti.com SCAS731B – NOVEMBER 2003 – REVISED JULY 2006 • FEATURES • • • • • • • • • 1 Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –55°C

lc08a

Abstract: SN54LVC08
Contextual Info: SN54LVC08A, SN74LVC08A QUADRUPLE 2-INPUT POSITIVE-AND GATES www.ti.com SCAS283P – JANUARY 1993 – REVISED AUGUST 2005 FEATURES 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 1B 1Y 2A 2B 2Y 1 14 2 13 4B 3 12 4A 4 11 4Y 5 10 3B 6 9 3A 7 8 SN54LVC08A . . . FK PACKAGE

Contextual Info: SN74LVC08A-EP QUADRUPLE 2-INPUT POSITIVE-AND GATE www.ti.com SCAS731C – NOVEMBER 2003 – REVISED MARCH 2007 • FEATURES • • • • • • • • • 1 Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –40°C

Contextual Info: SN74LVC08A-EP QUADRUPLE 2-INPUT POSITIVE-AND GATE www.ti.com SCAS731D – NOVEMBER 2003 – REVISED SEPTEMBER 2007 • FEATURES 1 • • • • • Controlled Baseline – One Assembly – One Test Site – One Fabrication Site Extended Temperature Performance of –40°C

SN74LVC08A

Contextual Info: SN74LVC08A QUADRUPLE 2-INPUT POSITIVE-AND GATE SCAS283C – JANUARY 1993 – REVISED SEPTEMBER 1996 D D D D D D D EPIC  Enhanced-Performance Implanted CMOS Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)

Contextual Info: SN74LVC08A-EP QUADRUPLE 2-INPUT POSITIVE-AND GATE www.ti.com SCAS731D – NOVEMBER 2003 – REVISED SEPTEMBER 2007 • FEATURES 1 • • • • • Controlled Baseline – One Assembly – One Test Site – One Fabrication Site Extended Temperature Performance of –40°C

Contextual Info: SN54LVC08A, SN74LVC08A www.ti.com SCAS283Q – JANUARY 1993 – REVISED OCTOBER 2010 QUADRUPLE 2-INPUT POSITIVE-AND GATES Check for Samples: SN54LVC08A, SN74LVC08A FEATURES 1 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 1B 1Y 2A 2B 2Y 14 1B 1A NC

Contextual Info: SN74LVC08A-EP QUADRUPLE 2-INPUT POSITIVE-AND GATE www.ti.com SCAS731D – NOVEMBER 2003 – REVISED SEPTEMBER 2007 • FEATURES 1 • • • • • Controlled Baseline – One Assembly – One Test Site – One Fabrication Site Extended Temperature Performance of –40°C

Contextual Info: SN74LVC08A-EP QUADRUPLE 2-INPUT POSITIVE-AND GATE www.ti.com SCAS731D – NOVEMBER 2003 – REVISED SEPTEMBER 2007 • FEATURES 1 • • • • • Controlled Baseline – One Assembly – One Test Site – One Fabrication Site Extended Temperature Performance of –40°C

LC08A top marking

Contextual Info: SN54LVC08A, SN74LVC08A QUADRUPLE 2-INPUT POSITIVE-AND GATES SCAS283L – JANUARY 1993 – REVISED JANUARY 2003 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 1B 1Y 2A 2B 2Y 14 1B 1A NC VCC 4B 1 2 SN54LVC08A . . . FK PACKAGE TOP VIEW 1Y NC 2A NC 2B

Contextual Info: SN74LVC08AĆEP QUADRUPLE 2ĆINPUT POSITIVEĆAND GATE SCAS731 − NOVEMBER 2003 D Controlled Baseline D D D D D D D D D − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of −40°C to 125°C Enhanced Diminishing Manufacturing

LC08A

Contextual Info: SN54LVC08A, SN74LVC08A QUADRUPLE 2-INPUT POSITIVE-AND GATES SCAS283M – JANUARY 1993 – REVISED JULY 2003 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 1B 1Y 2A 2B 2Y 14 1B 1A NC VCC 4B 1 2 SN54LVC08A . . . FK PACKAGE TOP VIEW 1Y NC 2A NC 2B 13 4B

LVC08A

Contextual Info: SN54LVC08A, SN74LVC08A QUADRUPLE 2-INPUT POSITIVE-AND GATES SCAS283L – JANUARY 1993 – REVISED JANUARY 2003 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 1B 1Y 2A 2B 2Y 14 1B 1A NC VCC 4B 1 2 SN54LVC08A . . . FK PACKAGE TOP VIEW 1Y NC 2A NC 2B

Contextual Info: SN74LVC08 QUADRUPLE 2-INPUT POSITIVE-AND GATE S C A S 2 8 3 -JANUARY 1993 - REVISED MARCH 1994 EPIC Enhanced-Performance Implanted CMOS Submicron Process D, DB, OR PW PACKAGE (TOP VIEW) Typical V q l p (Output Ground Bounce) < 0.8 V at Vcc = 3.3 V, TA = 25°C

SN74LVC08

Contextual Info: SN74LVC08 QUADRUPLE 2-INPUT POSITIVE-AND GATE S C A S 2 8 3 - JANUARY 1 9 9 3 -R E V IS E D MARCH 1994 D, DB, OR PW PACKAGE TOP VIEW EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Typical Vo lp (Output Ground Bounce) < 0.8 V at VCc = 3.3 V, TA = 25°C

lc08a

Abstract: A115-A C101 SN54LVC08A SN74LVC08A SN74LVC08APWR
Contextual Info: SN54LVC08A, SN74LVC08A QUADRUPLE 2-INPUT POSITIVE-AND GATES www.ti.com SCAS283P – JANUARY 1993 – REVISED AUGUST 2005 FEATURES 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 1B 1Y 2A 2B 2Y 1 14 2 13 4B 3 12 4A 4 11 4Y 5 10 3B 6 9 3A 7 8 SN54LVC08A . . . FK PACKAGE