SIL2105 Search Results

720 2001-01

Contextual Info: SIL2 S e r i e s • M in i-S IP Fast Rise Time, Low DCR Operating Specifications - Passive I*- i_ o Pulse Overshoot Pos . 5% to 10%, typical , Pulse Distortion ( S ) . 3% typical

sil2

Abstract: 125OC SIL2-2-55 SIL2-14-50 SIL2-5-75
Contextual Info: SIL2 Series Mini-SIP Passive Delay Modules Similar 3-pin SIP refer to SP3 Series Operating Specifications - Passive Delay Lines Fast Rise Time, Low DCR High Bandwidth 2-tap 4-pin SIP refer to SL2T Series 0.35 / tr Low Distortion LC Network Tight Delay Tolerance

SIL2

Abstract: SIL2-2T SL2T 125OC 720 2001-01
Contextual Info: SIL2 Series Mini-SIP Passive Delay Modules Operating Specifications - Passive Delay Lines Fast Rise Time, Low DCR High Bandwidth 0.35 / tr Low Distortion LC Network Tight Delay Tolerance Standard Impedances: 50 to 200 Ω Stable Delay vs. Temperature: 100 ppm/OC

Active (Logic Buffered)

Abstract: AML12-1 SP24L10005 SMD transistor M05 AMY-5 LVMDM-45G PLDM7-2.5 SMD 0505 RESISTOR 10K OHMS smd 2d 1002 -reel TZB4* "cross reference"
Contextual Info: Rhombus Industries Inc. 2001 Transformers & Magnetic Products Delay Lines Electromagnetic ∆t Logic Buffered Delay Low Distortion Buffered Input / Output Fast Rise Times 5V FAST/TTL & Advanced CMOS Single Output 5 Taps 10 Taps 16 Taps 20 Taps 3V Logic, Low Voltage CMOS

SIL2105

Abstract: SIP8 Package
Contextual Info: I SIL2 Style Schematic MiniS\P Passive Delay Modules ''T^ /T > 'T * SIL2 "3" Pin SIP Package 4 Pin package with unused pin removed ^ 1 2 3 IN COM OUT Detailed Dwg. See pg. 32, fig. 8 I Electrical Specifications at 25°C Delay (ns) Risa Time 20% - 80% max. (ns)

Delay Lines

Abstract: SMD 0505 RESISTOR 10K OHMS SMD transistor M05 equivalent ZO 607 TZB12-5 TF80 AMY-5 analog delay line schematic AML1-12-10 PLDM7-2.5
Contextual Info: Rhombus Industries Inc. 2002 Transformers & Magnetic Products Delay Lines Electromagnetic ∆t Logic Buffered Delay Low Distortion Buffered Input / Output Fast Rise Times 5V FAST/TTL & Advanced CMOS Single Output 5 Taps 10 Taps 16 Taps 20 Taps 3V Logic, Low Voltage CMOS

Contextual Info: Electrical Specifications at 25°C - See General Specifications top of page 13 Total ns Rise Time max. (ns) 1 ±.25 2 ±.25 3 ±.25 4 ±.25 5 ±.25 6 ±.25 7 ±.25 8 ±.25 9 ±.25 10 ±.25 11 ±.25 12 ±.25 15 ±.25 16 ±.30 20 ±.40 25 ±0.5 30 ±0.5 1.0