SFI4.2 Search Results

4 to 64 demux

Abstract: Mux/DeMux SFI-4.2 GR-253 SFI4.2 SFI4 Exar cross sfi4.1 GR-253-CORE PEB2756AE
Contextual Info: PEB2756AE TETHYS II QUAD STS-192/STM-64 MUX/DEMUX OCT 2009 REV. 1.0.0 GENERAL DESCRIPTION • Supports auto-detection of concatenation streams STS- Tethys™ II PEB2756AE is optimized for SONET/SDH applications as a full-duplex Quad SFI4.2 or Dual (SFI4.1) STS-192/STM-64 MUX/DEMUX with full

SFI4

Abstract: PEB2757AE STM-16 STM-64
Contextual Info: PEB2757AE TETHYS II 4 STS-192/STM-64, 16 STS-48/STM-16, MUX/DEMUX OCT 2009 REV. 1.0.0 GENERAL DESCRIPTION • Processes SONET/SDH sixteen STS-48/STM-16 or a Tethys™ II PEB2757AE is optimized for SONET/SDH applications as a full-duplex four channel SFI4.2 or

QSFP

Abstract: MPLS over optical packet switching OTU1 PDH/SDH stm 4 muxponder ethernet over sdh QSFP 40G transceiver stm 16 muxponder STM-16 Architecture ethernet over pdh
Contextual Info: Optical Transport Networks for 100G Implementation in FPGAs WP-01115-1.1 White Paper Based on announcements from vendors, enterprises and service providers, 100G system deployment is finally gaining real traction in the marketplace. The primary driver for this deployment is the customers’ ceaseless demand for higher bandwidth.

QT2225

Abstract: qt2025 s4886 S10124 G.975.1 QT2225-1 S4882 S4884 QT2025-1 S19262
Contextual Info: Transport Products Product Selector Guide Table of Contents Physical Layer Devices Framer/Mappers Datacom PHY S19225

RX-2C G

Abstract: tx2c transmitter TX 2E 1240 picosecond tx-2b equivalent Gigabyte 848 TX-2B RX-2B ROSENBERGER RX_2B XENPAK70
Contextual Info: Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide UG076 v4.1 November 2, 2008 R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the

CS2777

Abstract: SFI4 sfi-4 SFI-4.2
Contextual Info: CS2777 MILAN – OC192 Integrated MAC/Framer OVERVIEW Milan, CS2777, is an integrated MAC / Framer combining POS, GFP, ATM and RPR functionalities. It provides users a choice of line interfaces and is applicable in Metro Router and Switch applications. FEATURES

XR2206 application notes

Abstract: pin diagram of ic xr2206 IC XR2206 XR2206 XR2206 pin details for function generator XR2206 monolithic function generator xr2206 circuit peb1756ae fsk modulation and demodulation using Xr2206 MXP2
Contextual Info: Communications OTN Multi-Service OTN Muxponder/Mapper Ethernet Transport Ethernet over PDH Ethernet over SONET/SDH PDH over SONET/SDH Port Expanders SONET/SDH Multi-Ch/Multi-Rate Framer+Serdes Mappers + Framers Transceivers/CDR PDH E1 LIUs T1/E1/J1 LIUs BITS Solutions

G.975.1

Abstract: DDR3 layout OTN Framer MXP2 ODTU12 stm 4 muxponder CBR10G tt 6222-1 HD-SDI over sdh OTN SWITCH
Contextual Info: MXP2 Datasheet - G00676-07 20 Gb/s SONET/SDH/OTN Mapper and Multiplexor MXP2 20 Gb/s SONET/SDH/OTN Mapper and Multiplexor Document Number: G00676 Version Number: 7 Released on: 2 March 2011 Security: PROPRIETARY and CONFIDENTIAL PRELIMINARY EXAR Corporation and the EXAR Corporation logo are trademarks of EXAR Corporation.

GPON block diagram

Abstract: TSMC 40nm 90 nm hspice CEI-6G-SR CPRI multi rate 10Gcapable 29K212 pcie X1 edge connector sata CIRCUIT diagram 40G-100G
Contextual Info: Innovating With a Full Spectrum of 40-nm FPGAs and ASICs with Transceivers WP-01078-1.4 White Paper Increasing bandwidth requirements for broadband services are driving silicon vendors to use more and more high-speed serial transceivers. Therefore, nextgeneration applications feature a wide range of data rates, from a few Mbps to

Contextual Info: Product Brief Cortina Systems CS1777 OC-192c SONET/SDH Framer Product Description The Cortina Systems® CS1777 OC-192c SONET/SDH Framer CS1777 Framer with Integrated SerDes is an integrated SerDes/Framer combining POS, GFP, and ATM functionalities. It provides a choice of line interfaces used

PEB1757E

Abstract: GR-253 GR-253-CORE STS-192 PRBS-32
Contextual Info: PRELIMINARY PRODUCT FLYER Semiconductor Solutions for High Speed Communications and Fiber Optic Applications Tethys 4192 is optimized for SONET/SDH applications as a full-duplex four STS-192/STM-64 MUX/DEMUX with full framer functionality including pointer processing, and overhead termination; ideal for

to48c

Abstract: 1397-CBGA stm-64 to stm-1
Contextual Info: Tethys II SONET/SDH Multi-rate Framers OC-3/STM-1 to OC-192/ STM-64 Multi-Rate Solutions PEB2756AE/57AE Semiconductor Solutions for High Speed Communications and Fiber Optic Applications Features • • • • • • • • • • Differential CML 2.5 Gbps I/O interface

Transistor hall s41

Abstract: CEI-11G QSFP connector Xlaui 10 gbps transceiver board card fci tsmc design rule 40-nm QSFP QSFP 40G transceiver pcie gen3
Contextual Info: White Paper FPGAs at 40 nm and >10 Gbps: Jitter-, Signal Integrity-, Power-, and Process-Optimized Transceivers This paper describes key technologies that enable Stratix IV GT FPGAs to deliver the performance and capabilities necessary to support 40G/100G applications with integrated 11.3-Gbps transceivers. These include the LC-based oscillator and decision-feedback equalization DFE at 40 nm for ultra-low jitter FPGA transceivers. Furthermore, the

Contextual Info: Speedster22i SerDes User Guide UG028 – May 21, 2013 UG028, May 21, 2013 1 Table of Contents Table of Contents . 2 Table of Figures . 5

Contextual Info: CS1777 PALERMO – OC192/48 Framer with Integrated SerDes OVERVIEW Palermo, CS1777, is an integrated framer/serdes solution combining POS, GFP and ATM functionalities. It provides a choice of line interfaces applicable to router and switch applications. FEATURES

Contextual Info: TM Product Brief Cortina Systems CS2777 OC192 Integrated MAC/Framer Overview SPI-4.2 System Interface The Cortina Systems® CS2777 is an integrated MAC / Framer CS2777 MAC/Framer combining POS, GFP, ATM and RPR functionalities. It provides users a choice

UG-361

Abstract: 1000BASE-X DSP48E1 SRL16 VIRTEX-6 UG362 ds152 VIRTEX-6 UG360 lvdci18 Virtex 6 CXT FF484
Contextual Info: 52 Virtex-6 CXT Family Data Sheet DS153 v1.6 February 11, 2011 Product Specification General Description Virtex -6 CXT FPGAs provide designers needing power-optimized 3.75 Gb/s transceiver performance with an optimized ratio of built-in system-level blocks. These include 36 Kb block RAM/FIFOs, up to 15 Mb of block RAM, up to 768 DSP48E1

TSMC Flash 40nm

Abstract: CEI-6G-SR TSMC 40nm EP4SGX230F40 interlaken EP2AGX125F35 CPRI Multi Rate SAS controller chip 110G OTN fpga 10.7
Contextual Info: Full spectrum Simple bridging. Bandwidth-hungry, media-rich applications. Or something in between. No matter the scope, create your designs with the broadest portfolio of FPGAs and ASICs with transceivers. From low cost to the widest range of speeds and densities, you’ll have a full spectrum

2n2222 sot23

Abstract: g28 SOT23 j141c W17 sot23 j167 blm41pg471sn1l Transistor J182 J119 c495 C538
Contextual Info: LatticeSC Communications Platform Evaluation Board: LFSC25E-H-EV User’s Guide April 2007 Revision: ebug16_01.3 Lattice Semiconductor LatticeSC Communications Platform Evaluation Board: LFSC25E-H-EV User’s Guide Introduction This user’s guide describes the LatticeSC Communications Platform Evaluation Board featuring the LatticeSC 900fpBGA FPGA device. The stand-alone evaluation PCB provides a functional platform for development and rapid

tsmc cmos 0.13 um

Abstract: P802 10G serdes bert
Contextual Info: Preliminary Product Brief May 2003 SDM6G13 3 Gbits/s—6.25 Gbits/s Serializer/Deserializer Overview The SDM6G13 is a low-power 0.781 Gbits/s—6.25 Gbits/s backplane SerDes macrocell. Each 6.25 Gbits/s backplane channel provides an unprecedented combination of options, including the following:

G.975.1

Abstract: INTEL I7 microprocessor circuit diagram CS6001 cortina FC-1200 ULTRA FEC CS6001 CS6002 optical cross connect SDh, DWDM CS6005 rs255,239 FEC
Contextual Info: TM Product Brief Cortina Systems CS6001/2/3/4/5 Next Generation G.709 Optical Transport Processor Platform for 10G and 40G Product Overview Demand for bandwidth-intensive applications such as video-on-demand, music downloads, and telepresence is growing, and network deliv ery of larger file formats

Contextual Info: 4 Transceiver Configurations in Stratix V Devices 2013.05.06 SV52005 Subscribe Feedback Stratix V devices have a dedicated transceiver physical coding sublayer PCS and physical medium attachment (PMA) circuitry. To implement a protocol, use a PHY IP listed in Table 4-1.

GR-253

Abstract: PEB1757E GR-253-CORE STS-48 32 line demux T1X13
Contextual Info: Preliminary PEB1757E TETHYS 4192 QUAD STS-192/STM-64 MUX/DEMUX REV. P1.0.0 GENERAL DESCRIPTION Tethys™ 4192 is optimized for SONET/SDH applications as a full-duplex four STS-192/STM-64 MUX/ DEMUX with full framer functionality including pointer processing, and overhead termination; ideal for aggregation, ADM and DWDM applications. In the demultiplex ingress direction, Tethys™ 4192 accepts

TX240T

Abstract: interlaken "CT scan" Sarance Technologies Virtex-5 Ethernet development Virtex 5 for Network Card Virtex-5 LXT Ethernet FPGA Virtex 6 Ethernet virtex5 datasheets of optical fpgas
Contextual Info: Virtex-5 TXT Solutions Virtex-5 TXT FPGA Platform Single-FPGA Ultra-High Bandwidth Solutions The Challenges of Deploying Ultra-high Bandwidth Equipment • Not enough transceivers in a single device for high-performance networking, audio/video broadcast, and medical