SEMICONDUCTOR 4645 H Search Results

Contextual Info: SENSITRON SEMICONDUCTOR SHD120017 SHD120017P TECHNICAL DATA DATA SHEET 4645, REV. - HERMETIC SCHOTTKY RECTIFIER Very Low Forward Voltage Drop Features: • • • • • • Soft Reverse Recovery at Low and High Temperature Very Low Forward Voltage Drop

BD561

Contextual Info: HI5630 Semiconductor March 1999 Data Sheet Triple 8-Bit, 80MSPS A/D Converter with Internal Voltage Reference T he H I5630 is a m onolithic, triple 8-B it, 8 0 M S P S File Number 4645 Features • Triple 8-B it A /D C o nve rte r on a M o n o lith ic Chip

Contextual Info: FDP083N15A_F102 N-Channel PowerTrench MOSFET 150V, 105A, 8.3mW Features Description • RDS on = 6.85mW ( Typ.)@ VGS = 10V, ID = 75A This N-Channel MOSFET is produced using Fairchild Semiconductor’s advanced PowerTrench process that has been especially tailored to minimize the on-state resistance and yet

Contextual Info: FDB082N15A N-Channel PowerTrench MOSFET 150V, 105A, 8.2mW Features Description • RDS on = 6.7mW ( Typ.)@ VGS = 10V, ID = 75A This N-Channel MOSFET is produced using Fairchild Semiconductor’s advanced PowerTrench process that has been especially tailored to minimize the on-state resistance and yet

Contextual Info: FDP083N15A_F102 N-Channel PowerTrench MOSFET 150V, 105A, 8.3mΩ Features Description • RDS on = 6.85mΩ ( Typ.)@ VGS = 10V, ID = 75A This N-Channel MOSFET is produced using Fairchild Semiconductor’s advanced PowerTrench process that has been especially tailored to minimize the on-state resistance and yet

Contextual Info: FDB082N15A N-Channel PowerTrench MOSFET 150 V, 117 A, 8.2 mΩ Features Description • RDS on = 6.7 mΩ (Typ.) @ VGS = 10 V, ID = 75 A This N-Channel MOSFET is produced using Fairchild Semiconductor’s advance PowerTrench® process that has been tailored to minimize the on-state resistance while maintaining superior switching performance.

2217-33

Abstract: 33N capacitor TLV2217-33 TLV2217-33KC TLV2217-33N TLV2217-33PWLE TLV2217-33Y
Contextual Info: TLV2217-33, TLV2217-33Y LOW-DROPOUT 3.3-V FIXED VOLTAGE REGULATORS SLVS067B – MARCH 1992 – REVISED OCTOBER 1995 • • • • • • • • Fixed 3.3-V Output ± 1% Maximum Output Voltage Tolerance at TJ = 25°C 500 - mV Maximum Dropout Voltage at

AS7C1024

Abstract: AL205 AS7C31024 IN317
Contextual Info: Hi gh Per for m an ce 128K 128 K x8 C M OS S R A M A S 7C1024 A S 7C31024 1288K ×8 CMOS S R A M 12 Features • Organization: 131,072 words × 8 bits • High speed - 10/12/15/20 ns address access time - 3/3/4/5 ns output enable access time • Low power consumption

846C

Abstract: NTLTS3107P NTLTS3107PR2G
Contextual Info: NTLTS3107P Power MOSFET −20 V, −8.3 A, Single P−Channel, Micro8 Leadless Package Features • • • • • Low RDS on for Extended Battery Life Surface Mount Micro8 Leadless for Improved Thermal Performance Low Profile (<1.0 mm) Optimal for Portable Designs

CY7C130

Abstract: CY7C131 CY7C140 CY7C141 IDT7130 IDT7140 C1303 C1307
Contextual Info: CY7C130/CY7C131 CY7C140/CY7C141 1K x 8 DualĆPort Static RAM D Features D D D D speed/power Functional Description Automatic powerĆdown The CY7C130/CY7C131/CY7C140 and CY7C141 are highĆspeed CMOS 1K by 8 dualĆport static RAMs. Two ports are proĆ vided permitting independent access to

CY7C130

Abstract: CY7C131 CY7C140 CY7C141
Contextual Info: CY7C130/CY7C131 CY7C140/CY7C141 1K x 8 Dual-Port Static RAM Features Functional Description • True Dual-Ported memory cells which allow simultaneous reads of the same memory location • 1K x 8 organization • 0.65-micron CMOS for optimum speed/power • High-speed access: 15 ns

pi3hdmi301ffe

Abstract: PI3HDMI301
Contextual Info: ADVANCE INFORMATION - COMPANY CONFIDENTIAL PI3HDMI301 3:1 Active Switch for HDMITM signals with Optimized Equalization for Enhanced Signal Integrity Features Description • Supply voltage, VDD = 3.3V ±5% • Each of the three input ports can support HDMITM or DVI

MAX20024

Abstract: MA3810 ma 3810 MC10SX1130 receiver 4310 Nippon capacitors
Contextual Info: MOTOROLA Order this data sheet by MC10SX1130/D SEMICONDUCTOR TECHNICAL DATA LED Driver The MC10SX1130 is high speed LED Driver/current switch specifically targeted for use in FDDI PMD and ANSI X3T9.3 FibreChannel 266 Mbits/s optical transmitters. The integrated circuit contains several

Nippon capacitors

Contextual Info: MOTOROLA O rder th is data sheet by MC10SX1130/D SEMICONDUCTOR TECHNICAL DATA LED Driver The MC10SX1130 is high speed LED Driver/current switch specifically targeted for use in FDDI PMD and ANSI X3T9.3 FibreChannel 266 Mbits/s optical transmitters. The integrated circuit contains several

Contextual Info: DATA SHEET 1/11 1. Scope of Application This data sheet is applied to the LED package, model CLL040-1818A1-273M1A2. 2. Part code CLL 040 - 18 18 A1 - 27 3 M1 A2 [1] [2] [3] [4] [5] [6] [1] Part Code [2] Dies in series quantity [3] Dies in parallel quantity

C13220

Abstract: C1328 C1327 CY7C132 CY7C136 CY7C146 C1323 CY7C136-55NC
Contextual Info: CY7C132/CY7C136 CY7C142/CY7C146 2K x 8 DualĆPort Static RAM output enable OE . BUSY flags are proĆ vided on each port. In addition, an interĆ rupt flag (INT) is provided on each port of the 52Ćpin LCC and PLCC versions. BUSY signals that the port is trying to access the

C1307

Abstract: cY7c131 I CY7C130 CY7C131 CY7C140 CY7C141 C130-15 C1303 C13017
Contextual Info: fax id: 5200 1CY 7C14 0 CY7C130/CY7C131 CY7C140/CY7C141 1K x 8 Dual-Port Static Ram Features Functional Description • True Dual-Ported memory cells which allow simultaneous reads of the same memory location • 1K x 8 organization • 0.65-micron CMOS for optimum speed/power

C1303

Abstract: CY7C131 CY7C130 CY7C140 CY7C141
Contextual Info: 40 CY7C130/CY7C131 CY7C140/CY7C141 1K x 8 Dual-Port Static RAM Features Functional Description • True Dual-Ported memory cells which allow simultaneous reads of the same memory location • 1K x 8 organization • 0.65-micron CMOS for optimum speed/power

Contextual Info: CY7C130, CY7C130A CY7C131, CY7C131A 1 K x 8 Dual-Port Static RAM 1 K × 8 Dual-Port Static RAM Functional Description Features • True dual-ported memory cells, which allow simultaneous reads of the same memory location ■ 1 K × 8 organization ■ 0.65 micron CMOS for optimum speed and power

Contextual Info: fax id: 5200 CY7C130/CY7C131 CY7C140/CY7C141 W CYPRESS 1K x 8 Dual-Port Static Ram Features Functional Description True Dual-Ported memory cells which allow simulta­ neous reads of the same memory location 1K x 8 organization 0.65-micron CMOS for optimum speed/power

AS4LC1M16S1

Abstract: AS4LC1M16S0 A102BA
Contextual Info: May 2001 AS4LC2M8S1 AS4LC2M8S0 AS4LC1M16S1 AS4LC1M16S0 Preliminary 3.3V 2M x 8/1M × 16 CMOS synchronous DRAM Features • Organization - 1,048,576 words × 8 bits × 2 banks 2M × 8 11 row, 9 column address - 524,288 words × 16 bits × 2 banks (1M × 16)

80960JT

Abstract: 80960RM 80960RP GC80960RM100 273156 af-3230
Contextual Info: 80960RM I/O Processor • ■ Complies with PCI Local Bus Specification, Revision 2.1 5 V, PCI Signalling Environment Data Sheet Advance Information Product Features ■ ■ ■ ■ High Performance 80960JT Core ■ — Sustained One Instruction/Clock Execution

pic18 an953

Abstract: 4558 dd 97120 lfsr galois prbs using lfsr 811b fc 4558 DS00821 f 4558 MOV1
Contextual Info: AN953 Data Encryption Routines for the PIC18 Author: David Flowers Microchip Technology Inc. INTRODUCTION This Application Note covers four encryption algorithms: AES, XTEA, SKIPJACK and a simple encryption algorithm using a pseudo-random binary sequence generator. The science of cryptography

540L

Contextual Info: 80960RM I/O Processor • Complies with PCI Local Bus Specification, Revision 2.1 ■ 5 K PCI Signalling Environment Data Sheet Advance Information Product Features ■ High Performance 80960JT Core ■ — Sustained One Instruction/Clock Execution — 16 Kbyte, Two-Way Set-Associative