SSTV16857
Abstract: AN-5016 IBIS versus measured data measured data versus IBIS PC133 registered reference design transistor 5016
Text: Fairchild Semiconductor Application Note August 2000 Revised June 2001 Double Data Rate Support ICs Introduction Today’s latest developments in chipset and motherboard design have pushed beyond the bandwidth of conventional PC100/PC133 SDRAM; the next stage of evolutionary
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PC100/PC133)
SSTV16857
AN-5016
IBIS versus measured data
measured data versus IBIS
PC133 registered reference design
transistor 5016
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PCI 6140-AA33PC G
Abstract: PQFP-128 footprint PCI 6140-AA33PC FIREWIRE 800 USB ethernet bridge PQFP-128 usb to midi RS-232 IBIS models 6140 USB to ethernet bridge
Text: Issue No. 14 PCI 6140 Key Features ♦ Lowest cost FastLaneTM Bridge ♦ 200mW Power Consumption ♦ Small Footprint PQFP-128 Package ♦ Lead Free Available ♦ Low Latency Other Important Features ♦ 3.3V signaling, including 5V input signal tolerance ♦ Hot swap friendly
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200mW
PQFP-128
6140-Combo-EA-1
PCI 6140-AA33PC G
PQFP-128 footprint
PCI 6140-AA33PC
FIREWIRE 800
USB ethernet bridge
PQFP-128
usb to midi
RS-232 IBIS models
6140
USB to ethernet bridge
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lf1300
Abstract: LF412CN
Text: MICROCIRCUIT DATA SHEET Original Creation Date: 05/02/95 Last Update Date: 04/14/98 Last Major Revision Date: 05/02/95 MNLF412-X REV 0C1 LOW OFFSET, LOW DRIFT DUAL JFET INPUT OPERATIONAL AMPLIFIER General Description These devices are low cost, high speed, JFET input operational amplifiers with very low
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MNLF412-X
LF412
LM1558,
4-Nov-95
24-Feb99
9-Apr-96
lf1300
LF412CN
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TMS320Lx240x
Abstract: vp231
Text: SN65HVD230 SN65HVD231 SN65HVD232 SLOS346F – MARCH 2001 – REVISED OCTOBER 2001 3.3 V CAN TRANSCEIVERS FEATURES D Operates With a 3.3-V Supply D Low Power Replacement for the PCA82C250 D D D D D D D D D D D Footprint Bus/Pin ESD Protection Exceeds 16 kV HBM
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SN65HVD230
SN65HVD231
SN65HVD232
SLOS346F
PCA82C250
Powe/09/2001)
TMS320Lx240x
vp231
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LM3046M
Abstract: on semiconductor "Transistor Arrays"
Text: LM3046 Transistor Array General Description Features The LM3046 consists of five general purpose silicon NPN transistors on a common monolithic substrate. Two of the transistors are internally connected to form a differentially-connected pair. The transistors are well suited
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LM3046
14-lead
AN-299:
24-Feb-99
5-Aug-2002]
LM3046M
on semiconductor "Transistor Arrays"
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"Op Amp" 311
Abstract: LF412CN
Text: LF412 Low Offset, Low Drift Dual JFET Input Operational Amplifier General Description Features These devices are low cost, high speed, JFET input operational amplifiers with very low input offset voltage and guaranteed input offset voltage drift. They require low supply current yet maintain a large gain bandwidth product and fast
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LF412
LM1558,
conve2000]
24View
Feb-99
"Op Amp" 311
LF412CN
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RTSX32su
Abstract: Actel a54sx72a tid Silicon Sculptor II
Text: v2.2 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case
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TM1019
RTSX32su
Actel a54sx72a tid
Silicon Sculptor II
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RTSX72
Abstract: No abstract text available
Text: v2.2 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case
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TM1019
RTSX72
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RTSX32SU CQ84
Abstract: Silicon Sculptor II RTSX32SU actel 1020
Text: v2.1 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case
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TM1019
RTSX32SU CQ84
Silicon Sculptor II
RTSX32SU
actel 1020
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RTSX32SU
Abstract: RTSX32SU CQ84 Actel a54sx72a tid RTSX72SU RTSX-SU actel 1020 Silicon Sculptor II actel 1020 datasheet RT54SX E11213
Text: v2.2 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case
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TM1019
RTSX32SU
RTSX32SU CQ84
Actel a54sx72a tid
RTSX72SU
RTSX-SU
actel 1020
Silicon Sculptor II
actel 1020 datasheet
RT54SX
E11213
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LF412
Abstract: LF412A LF412CN LF412ch
Text: LF412 Low Offset, Low Drift Dual JFET Input Operational Amplifier General Description Features These devices are low cost, high speed, JFET input operational amplifiers with very low input offset voltage and guaranteed input offset voltage drift. They require low supply current yet maintain a large gain bandwidth product and fast
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LF412
LM1558,
24-Feb-99
4-Nov-95
9-Apr-96
AN-447:
LF412A
LF412CN
LF412ch
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412CN
Abstract: LF412 LM15 AN447 LF412CN
Text: LF412 Low Offset, Low Drift Dual JFET Input Operational Amplifier General Description Features These devices are low cost, high speed, JFET input operational amplifiers with very low input offset voltage and guaranteed input offset voltage drift. They require low supply current yet maintain a large gain bandwidth product and fast
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LF412
LM1558,
4-Nov-95
24-Feb99
9-Apr-96
412CN
LM15
AN447
LF412CN
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PDF
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lf412
Abstract: LF412CN
Text: LF412 Low Offset, Low Drift Dual JFET Input Operational Amplifier General Description Features These devices are low cost, high speed, JFET input operational amplifiers with very low input offset voltage and guaranteed input offset voltage drift. They require low supply current yet maintain a large gain bandwidth product and fast
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LF412
LM1558,
4-Nov-95
24-Feb-99
9-Apr-96
LF412CN
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RTSX32SU
Abstract: RTSX32SU CQ84 rtsx72su RTSX32 RTSX-SU 1/RTSX32su CC256 PRB-1 actel 1020 datasheet CG624
Text: Revision 7 RTSX-SU RadTolerant FPGAs UMC FuseLock Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case
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TM1019
MIL-ST00
RTSX32SU
RTSX32SU CQ84
rtsx72su
RTSX32
RTSX-SU
1/RTSX32su
CC256
PRB-1
actel 1020 datasheet
CG624
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RTSX32SU CQ84 PROTO
Abstract: RTSX32SU CQ84 RTSX72SU1 SOC 8A fuse smd RTSX32su CG624 thermal expansion
Text: Revision 9 RTSX-SU Radiation-Tolerant FPGAs UMC Designed for Space • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single Event Upsets (SEU) to LETth > 40 MeVcm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case
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TM1019
RTSX32SU CQ84 PROTO
RTSX32SU CQ84
RTSX72SU1
SOC 8A fuse smd
RTSX32su
CG624 thermal expansion
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SMD ARAY
Abstract: No abstract text available
Text: Revision 6 RTSX-SU RadTolerant FPGAs UMC FuseLock Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case
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TM1019
MIL-STD-883B
SMD ARAY
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A2F200M3F-FG256
Abstract: A2F200M3F a2f50 b20 100 transister CS288 A2F060 A2F500 A2F200-FG484 transister di 505 AES128
Text: Revision 4 Actel’s SmartFusion Intelligent Mixed Signal FPGAs Microcontroller Subsystem MSS • • • • • • • • • • • • Hard 100 MHz 32-Bit ARM Cortex -M3 – 1.25 DMIPS/MHz Throughput from Zero Wait State Memory – Memory Protection Unit (MPU)
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32-Bit
Ba600
A2F200M3F-FG256
A2F200M3F
a2f50
b20 100 transister
CS288
A2F060
A2F500
A2F200-FG484
transister di 505
AES128
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Untitled
Abstract: No abstract text available
Text: Revision 13 IGLOOe Low Power Flash FPGAs with Flash*Freeze Technology Features and Benefits Low Power • • • • 1.2 V to 1.5 V Core Voltage Support for Low Power Supports Single-Voltage System Operation Low-Power Active FPGA Operation Flash*Freeze Technology
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130-nm,
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Untitled
Abstract: No abstract text available
Text: Revision 12 IGLOOe Low Power Flash FPGAs with Flash*Freeze Technology Features and Benefits Low Power • • • • 1.2 V to 1.5 V Core Voltage Support for Low Power Supports Single-Voltage System Operation Low-Power Active FPGA Operation Flash*Freeze Technology
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Untitled
Abstract: No abstract text available
Text: Revision 11 IGLOOe Low Power Flash FPGAs with Flash*Freeze Technology Features and Benefits Low Power • • • • 1.2 V to 1.5 V Core Voltage Support for Low Power Supports Single-Voltage System Operation Low-Power Active FPGA Operation Flash*Freeze Technology
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130-nm,
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Untitled
Abstract: No abstract text available
Text: Revision 9 IGLOOe Low Power Flash FPGAs with Flash*Freeze Technology Features and Benefits Low Power • • • • 1.2 V to 1.5 V Core Voltage Support for Low Power Supports Single-Voltage System Operation Low-Power Active FPGA Operation Flash*Freeze Technology
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Untitled
Abstract: No abstract text available
Text: Revision 12 IGLOOe Low Power Flash FPGAs with Flash*Freeze Technology Features and Benefits Low Power • • • • 1.2 V to 1.5 V Core Voltage Support for Low Power Supports Single-Voltage System Operation Low-Power Active FPGA Operation Flash*Freeze Technology
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130-nm,
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A2F500-FG484
Abstract: soc 1044 A2F060
Text: Revision 1 Military Grade SmartFusion Customizable System-on-Chip cSoC Product Benefits • • 100% Military Temperature Tested and Qualified from –55°C to 125°C Not Susceptible to Neutron-Induced Configuration Loss Microcontroller Subsystem (MSS) •
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32-Bit
A2F500-FG484
soc 1044
A2F060
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Untitled
Abstract: No abstract text available
Text: Revision 0 Military Grade SmartFusion Customizable System-on-Chip cSoC Product Benefits • • 100% Military Temperature Tested and Qualified from –55°C to 125°C Not Susceptible to Neutron-Induced Configuration Loss Microcontroller Subsystem (MSS) •
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