100LQ128
Abstract: 2096E 2096E180LT
Text: ispLSI 2096E In-System Programmable SuperFAST High Density PLD Features Functional Block Diagram Output Routing Pool ORP Output Routing Pool (ORP) C7 C5 C4 Output Routing Pool (ORP) C3 C2 C1 C0 A0 B7 D Q A1 A2 GLB Logic Array B6 D Q Global Routing Pool
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2096E
0212/2096E
2096E
2096E-180LT128
128-Pin
2096E-180LQ128
2096E-135LT128
100LQ128
2096E180LT
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2096E
Abstract: No abstract text available
Text: ispLSI 2096E In-System Programmable SuperFAST High Density PLD Features Functional Block Diagram Output Routing Pool ORP Output Routing Pool (ORP) C7 C5 C4 Output Routing Pool (ORP) C3 C2 C1 C0 A0 B7 D Q A1 A2 GLB Logic Array B6 D Q Global Routing Pool
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2096E
0212/2096E
2096E
2096E-180LT128
128-Pin
2096E-180LQ128
2096E-135LT128
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2096E
Abstract: No abstract text available
Text: ispLSI 2096E In-System Programmable SuperFAST High Density PLD Features Functional Block Diagram Output Routing Pool ORP Output Routing Pool (ORP) C7 C5 C4 Output Routing Pool (ORP) C3 C2 C1 C0 A0 B7 D Q A1 A2 GLB Logic Array B6 D Q Global Routing Pool
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2096E
0212/2096E
2096E
2096E-180LT128
128-Pin
2096E-180LQ128
2096E-135LT128
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2192VE-135LB144
Abstract: No abstract text available
Text: ispLSI 2192VE 3.3V In-System Programmable SuperFAST High Density PLD Functional Block Diagram Output Routing Pool Output Routing Pool F7 F6 F5 F4 F3 F2 F1 F0 E7 E6 E5 E4 E3 E2 E1 E0 D7 Output Routing Pool A0 D Q A1 A2 A3 A4 Logic Global Routing Pool GRP
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2192VE
2096VE
225MHz
128-Pin
144-Ball
0212B/2192VE
2192VE
2192VE-225LT128
2192VE-225LB144
2192VE-180LT128*
2192VE-135LB144
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2096VE
Abstract: 2192VE IN6112
Text: ispLSI 2192VE 3.3V In-System Programmable SuperFAST High Density PLD Functional Block Diagram Output Routing Pool Output Routing Pool F7 F6 F5 F4 F3 F2 F1 F0 E7 E6 E5 E4 E3 E2 E1 E0 D7 Output Routing Pool A0 D Q A1 A2 A3 A4 Logic Global Routing Pool GRP
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2192VE
2192VE-225LT128
128-Pin
2192VE-225LB144
144-Ball
2192VE-180LT128*
2192VE-180LB144*
2192VE-135LT128
2096VE
2192VE
IN6112
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2192VE100LT
Abstract: 2096VE 2192VE
Text: ispLSI 2192VE 3.3V In-System Programmable SuperFAST High Density PLD Functional Block Diagram Output Routing Pool Output Routing Pool F7 F6 F5 F4 F3 F2 F1 F0 E7 E6 E5 E4 E3 E2 E1 E0 D7 Output Routing Pool A0 D Q A1 A2 A3 A4 Logic Global Routing Pool GRP
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2192VE
2192VE-225LT128
128-Pin
2192VE-225LB144
144-Ball
2192VE-180LT128*
2192VE-180LB144*
2192VE-135LT128
2192VE100LT
2096VE
2192VE
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2096VE
Abstract: 2192VE
Text: LeadFree Package Options Available! 3.3V In-System Programmable SuperFAST High Density PLD Functional Block Diagram Output Routing Pool Output Routing Pool F7 F6 F5 F4 F3 F2 F1 F0 E7 E6 E5 E4 E3 E2 E1 E0 D7 Output Routing Pool A0 D Q A1 A2 A3 A4 Logic Global Routing Pool GRP
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2192VE-100LB144
144-Ball
2-0041D/2192VE
2192VE-225
2192VE-180LT128I
128-Pin
041A/2192VE
2192VE-225LTN128
2192VE-135LTN128
2096VE
2192VE
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Untitled
Abstract: No abstract text available
Text: ispLSI and pLSI 1048 ® High-Density Programmable Logic Functional Block Diagram Output Routing Pool E7 E6 E5 E4 E3 E2 E1 E0 S Output Routing Pool F7 F6 F5 F4 F3 F2 F1 F0 D Q A2 A3 A4 Logic Global Routing Pool GRP Array ES Output Routing Pool A0 A1 A5
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0212-80B-isp1048
120-Pin
1048-70LQ
1048-50LQ
1048-80LQ
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2096VE
Abstract: 2192VE IN6112
Text: ispLSI 2192VE 3.3V In-System Programmable SuperFAST High Density PLD Functional Block Diagram Output Routing Pool Output Routing Pool F7 F6 F5 F4 F3 F2 F1 F0 E7 E6 E5 E4 E3 E2 E1 E0 D7 Output Routing Pool A0 D Q A1 A2 A3 A4 Logic Global Routing Pool GRP
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2192VE
0212B/2192VE
2192VE
2192VE-225LT128*
128-Pin
2192VE-225LB144*
144-Ball
2192VE-180LT128*
2192VE-180LB144*
2096VE
IN6112
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Untitled
Abstract: No abstract text available
Text: Agilent N2X IPv4 Routing Emulation Software E7882A Technical Data Sheet Agilent N2X IPv4 Routing Emulation Software integrates the most scalable BGP-4, OSPF, IS-IS and RIP routing protocol emulations available to deliver unparalleled protocol verification and
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E7882A
E7882A
5988-9950EN
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0212-80B-isp1048
Abstract: 1048E 1048-80L
Text: ispLSI 1048 In-System Programmable High Density PLD Functional Block Diagram Output Routing Pool E7 E6 E5 E4 E3 E2 E1 E0 Output Routing Pool A0 D Q A1 A2 A3 A4 S Output Routing Pool F7 F6 F5 F4 F3 F2 F1 F0 Logic Global Routing Pool GRP A5 Array D Q D Q
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0212-80B-isp1048
120-Pin
1048-70LQ
1048-50LQ
1048-80LQ
1048-50LQI
041A-48-isp
0212-80B-isp1048
1048E
1048-80L
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TGMR
Abstract: PT80 T-type flip flop
Text: 8000 Family Architectural Description Outputs from the GLBs in a Big Fast Megablock can drive both the Big Fast Megablock Routing Pool within the Big Fast Megablock and the Global Routing Plane between the Big Fast Megablocks. Switching resources are provided to allow signals in the Global Routing Plane to drive
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router
Abstract: 5988-9950EN bgp route flap route messages protocol "BGP" "Border Gateway Protocol" "OSPF" "LINK STATE"
Text: Agilent N2X IPv4 Routing Emulation Software E7882A Technical Data Sheet Agilent N2X IPv4 Routing Emulation Software integrates the most scalable BGP-4, OSPF, IS-IS and RIP routing protocol emulations available to deliver unparalleled protocol verification and
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E7882A
E7882A
5988-9950EN
router
5988-9950EN
bgp route flap
route messages protocol
"BGP"
"Border Gateway Protocol"
"OSPF"
"LINK STATE"
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PT80
Abstract: No abstract text available
Text: 8000 and 8000V Family Architectural Description Outputs from the GLBs in a Big Fast Megablock can drive both the Big Fast Megablock Routing Pool within the Big Fast Megablock and the Global Routing Plane between the Big Fast Megablocks. Switching resources are provided to allow signals in the Global Routing Plane to drive
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PCM9211
Abstract: No abstract text available
Text: PCM9211 www.ti.com SBAS495 – JUNE 2010 216-kHz Digital Audio Interface Transceiver DIX with Stereo ADC and Routing Check for Samples: PCM9211 FEATURES 1 • Integrated DIX, ADC, and Signal Routing: – Asynchronous Operation (DIR, DIT, ADC) – Mux and Routing of PCM Data:
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PCM9211
SBAS495
216-kHz
24-bit,
50-ps
IEC61937,
PCM9211
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Untitled
Abstract: No abstract text available
Text: PCM9211 www.ti.com SBAS495 – JUNE 2010 216-kHz Digital Audio Interface Transceiver DIX with Stereo ADC and Routing Check for Samples: PCM9211 FEATURES 1 • Integrated DIX, ADC, and Signal Routing: – Asynchronous Operation (DIR, DIT, ADC) – Mux and Routing of PCM Data:
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PCM9211
SBAS495
216-kHz
24-bit,
50-ps
IEC61937,
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pcm9211
Abstract: SBAS495
Text: PCM9211 www.ti.com SBAS495 – JUNE 2010 216-kHz Digital Audio Interface Transceiver DIX with Stereo ADC and Routing Check for Samples: PCM9211 FEATURES 1 • Integrated DIX, ADC, and Signal Routing: – Asynchronous Operation (DIR, DIT, ADC) – Mux and Routing of PCM Data:
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PCM9211
SBAS495
216-kHz
24-bit,
50-ps
IEC61937,
pcm9211
SBAS495
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Untitled
Abstract: No abstract text available
Text: PCM9211 www.ti.com SBAS495 – JUNE 2010 216-kHz Digital Audio Interface Transceiver DIX with Stereo ADC and Routing Check for Samples: PCM9211 FEATURES 1 • Integrated DIX, ADC, and Signal Routing: – Asynchronous Operation (DIR, DIT, ADC) – Mux and Routing of PCM Data:
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PCM9211
SBAS495
216-kHz
24-bit,
50-ps
IEC61937,
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GR-1110-CORE
Abstract: No abstract text available
Text: PM7322 RCMP-800 STANDARD PRODUCT PMC-940904, ISSUE 6 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps PM7322 RCMP-800 ATM LAYER ROUTING CONTROL, MONITORING AND
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PM7322
RCMP-800
PMC-940904,
PMC-940904
PMC-940903
GR-1110-CORE
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PM7322-SI
Abstract: GR-1110-CORE PMC-940904 PM7322 RCMP-800 PM7322SI
Text: PM7322 RCMP-800 STANDARD PRODUCT PMC-940904, ISSUE 6 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps PM7322 RCMP-800 ATM LAYER ROUTING CONTROL, MONITORING AND
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PM7322
RCMP-800
PMC-940904,
PM7322
PMC-940904
PMC-940903
PM7322-SI
GR-1110-CORE
RCMP-800
PM7322SI
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Ternary CAM
Abstract: mmi av
Text: ADVANCE Melody Routing Coprocessor MELODY ROUTING COPROCESSOR RCP FAMILY 4K: MT75L4L32MLQ 8K: MT75L8L32MLQ For the latest data sheet, please refer to the Micron Web site: www.micron.com/datasheets GENERAL DESCRIPTION The Melody RCP family consists of 4K and 8K x 64bit Routing Coprocessors (RCPs) with a 32-bit wide
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64bit
32-bit
March/13/02/
Mar/06/02
Ternary CAM
mmi av
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1048C
Abstract: No abstract text available
Text: Specifications ispLSI and pLSI 1048C ispLSI and pLSI 1048C ® High-Density Programmable Logic Functional Block Diagram Output Routing Pool Output Routing Pool F7 F6 F5 F4 F3 F2 F1 F0 E7 E6 E5 E4 E3 E2 E1 E0 D7 A2 A4 IG N D Q Logic Global Routing Pool GRP
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1048C
Military/883
1048C
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Untitled
Abstract: No abstract text available
Text: Specifications ispLSI and pLSI 1048 ispLSI and pLSI 1048 ® High-Density Programmable Logic Functional Block Diagram Output Routing Pool E7 E6 E5 E4 E3 E2 E1 E0 S Output Routing Pool F7 F6 F5 F4 F3 F2 F1 F0 D Q A2 A3 A4 Logic Global Routing Pool GRP Array
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20041A
Abstract: 2064VE 2064VL
Text: ispLSI 2064VL Features Functional Block Diagram • SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC • • • Input Bus Output Routing Pool ORP Input Bus A1 Logic Array B3 B2 D Q GLB B4 D Q B1 D Q D Q Input Bus Global Routing Pool (GRP) A0 A2 B5 Output Routing Pool (ORP)
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2064VL
2064VE
2064VL-135LT44
44-Pin
2064VL-100LT100
100-Pin
2064VL-100LB100
100-Ball
2064VL-100LJ44
20041A
2064VL
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