ROUTING SWITCHING Search Results

100LQ128

Abstract: 2096E 2096E180LT
Contextual Info: ispLSI 2096E In-System Programmable SuperFAST High Density PLD Features Functional Block Diagram Output Routing Pool ORP Output Routing Pool (ORP) C7 C5 C4 Output Routing Pool (ORP) C3 C2 C1 C0 A0 B7 D Q A1 A2 GLB Logic Array B6 D Q Global Routing Pool

2096E

Contextual Info: ispLSI 2096E In-System Programmable SuperFAST High Density PLD Features Functional Block Diagram Output Routing Pool ORP Output Routing Pool (ORP) C7 C5 C4 Output Routing Pool (ORP) C3 C2 C1 C0 A0 B7 D Q A1 A2 GLB Logic Array B6 D Q Global Routing Pool

2096E

Contextual Info: ispLSI 2096E In-System Programmable SuperFAST High Density PLD Features Functional Block Diagram Output Routing Pool ORP Output Routing Pool (ORP) C7 C5 C4 Output Routing Pool (ORP) C3 C2 C1 C0 A0 B7 D Q A1 A2 GLB Logic Array B6 D Q Global Routing Pool

2192VE-135LB144

Contextual Info: ispLSI 2192VE 3.3V In-System Programmable SuperFAST High Density PLD Functional Block Diagram Output Routing Pool Output Routing Pool F7 F6 F5 F4 F3 F2 F1 F0 E7 E6 E5 E4 E3 E2 E1 E0 D7 Output Routing Pool A0 D Q A1 A2 A3 A4 Logic Global Routing Pool GRP

2096VE

Abstract: 2192VE IN6112
Contextual Info: ispLSI 2192VE 3.3V In-System Programmable SuperFAST High Density PLD Functional Block Diagram Output Routing Pool Output Routing Pool F7 F6 F5 F4 F3 F2 F1 F0 E7 E6 E5 E4 E3 E2 E1 E0 D7 Output Routing Pool A0 D Q A1 A2 A3 A4 Logic Global Routing Pool GRP

2192VE100LT

Abstract: 2096VE 2192VE
Contextual Info: ispLSI 2192VE 3.3V In-System Programmable SuperFAST High Density PLD Functional Block Diagram Output Routing Pool Output Routing Pool F7 F6 F5 F4 F3 F2 F1 F0 E7 E6 E5 E4 E3 E2 E1 E0 D7 Output Routing Pool A0 D Q A1 A2 A3 A4 Logic Global Routing Pool GRP

2096VE

Abstract: 2192VE
Contextual Info: LeadFree Package Options Available! 3.3V In-System Programmable SuperFAST High Density PLD Functional Block Diagram Output Routing Pool Output Routing Pool F7 F6 F5 F4 F3 F2 F1 F0 E7 E6 E5 E4 E3 E2 E1 E0 D7 Output Routing Pool A0 D Q A1 A2 A3 A4 Logic Global Routing Pool GRP

Contextual Info: ispLSI and pLSI 1048 ® High-Density Programmable Logic Functional Block Diagram Output Routing Pool E7 E6 E5 E4 E3 E2 E1 E0 S Output Routing Pool F7 F6 F5 F4 F3 F2 F1 F0 D Q A2 A3 A4 Logic Global Routing Pool GRP Array ES Output Routing Pool A0 A1 A5

2096VE

Abstract: 2192VE IN6112
Contextual Info: ispLSI 2192VE 3.3V In-System Programmable SuperFAST High Density PLD Functional Block Diagram Output Routing Pool Output Routing Pool F7 F6 F5 F4 F3 F2 F1 F0 E7 E6 E5 E4 E3 E2 E1 E0 D7 Output Routing Pool A0 D Q A1 A2 A3 A4 Logic Global Routing Pool GRP

Contextual Info: Agilent N2X IPv4 Routing Emulation Software E7882A Technical Data Sheet Agilent N2X IPv4 Routing Emulation Software integrates the most scalable BGP-4, OSPF, IS-IS and RIP routing protocol emulations available to deliver unparalleled protocol verification and

0212-80B-isp1048

Abstract: 1048E 1048-80L
Contextual Info: ispLSI 1048 In-System Programmable High Density PLD Functional Block Diagram Output Routing Pool E7 E6 E5 E4 E3 E2 E1 E0 Output Routing Pool A0 D Q A1 A2 A3 A4 S Output Routing Pool F7 F6 F5 F4 F3 F2 F1 F0 Logic Global Routing Pool GRP A5 Array D Q D Q

TGMR

Abstract: PT80 T-type flip flop
Contextual Info: 8000 Family Architectural Description Outputs from the GLBs in a Big Fast Megablock can drive both the Big Fast Megablock Routing Pool within the Big Fast Megablock and the Global Routing Plane between the Big Fast Megablocks. Switching resources are provided to allow signals in the Global Routing Plane to drive

router

Abstract: 5988-9950EN bgp route flap route messages protocol "BGP" "Border Gateway Protocol" "OSPF" "LINK STATE"
Contextual Info: Agilent N2X IPv4 Routing Emulation Software E7882A Technical Data Sheet Agilent N2X IPv4 Routing Emulation Software integrates the most scalable BGP-4, OSPF, IS-IS and RIP routing protocol emulations available to deliver unparalleled protocol verification and

PT80

Contextual Info: 8000 and 8000V Family Architectural Description Outputs from the GLBs in a Big Fast Megablock can drive both the Big Fast Megablock Routing Pool within the Big Fast Megablock and the Global Routing Plane between the Big Fast Megablocks. Switching resources are provided to allow signals in the Global Routing Plane to drive

PCM9211

Contextual Info: PCM9211 www.ti.com SBAS495 – JUNE 2010 216-kHz Digital Audio Interface Transceiver DIX with Stereo ADC and Routing Check for Samples: PCM9211 FEATURES 1 • Integrated DIX, ADC, and Signal Routing: – Asynchronous Operation (DIR, DIT, ADC) – Mux and Routing of PCM Data:

Contextual Info: PCM9211 www.ti.com SBAS495 – JUNE 2010 216-kHz Digital Audio Interface Transceiver DIX with Stereo ADC and Routing Check for Samples: PCM9211 FEATURES 1 • Integrated DIX, ADC, and Signal Routing: – Asynchronous Operation (DIR, DIT, ADC) – Mux and Routing of PCM Data:

pcm9211

Abstract: SBAS495
Contextual Info: PCM9211 www.ti.com SBAS495 – JUNE 2010 216-kHz Digital Audio Interface Transceiver DIX with Stereo ADC and Routing Check for Samples: PCM9211 FEATURES 1 • Integrated DIX, ADC, and Signal Routing: – Asynchronous Operation (DIR, DIT, ADC) – Mux and Routing of PCM Data:

Contextual Info: PCM9211 www.ti.com SBAS495 – JUNE 2010 216-kHz Digital Audio Interface Transceiver DIX with Stereo ADC and Routing Check for Samples: PCM9211 FEATURES 1 • Integrated DIX, ADC, and Signal Routing: – Asynchronous Operation (DIR, DIT, ADC) – Mux and Routing of PCM Data:

GR-1110-CORE

Contextual Info: PM7322 RCMP-800 STANDARD PRODUCT PMC-940904, ISSUE 6 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps PM7322 RCMP-800 ATM LAYER ROUTING CONTROL, MONITORING AND

PM7322-SI

Abstract: GR-1110-CORE PMC-940904 PM7322 RCMP-800 PM7322SI
Contextual Info: PM7322 RCMP-800 STANDARD PRODUCT PMC-940904, ISSUE 6 ROUTING CONTROL, MONITORING AND POLICING 800 Mbps PM7322 RCMP-800 ATM LAYER ROUTING CONTROL, MONITORING AND

Ternary CAM

Abstract: mmi av
Contextual Info: ADVANCE Melody Routing Coprocessor MELODY ROUTING COPROCESSOR RCP FAMILY 4K: MT75L4L32MLQ 8K: MT75L8L32MLQ For the latest data sheet, please refer to the Micron Web site: www.micron.com/datasheets GENERAL DESCRIPTION The Melody RCP family consists of 4K and 8K x 64bit Routing Coprocessors (RCPs) with a 32-bit wide

1048C

Contextual Info: Specifications ispLSI and pLSI 1048C ispLSI and pLSI 1048C ® High-Density Programmable Logic Functional Block Diagram Output Routing Pool Output Routing Pool F7 F6 F5 F4 F3 F2 F1 F0 E7 E6 E5 E4 E3 E2 E1 E0 D7 A2 A4 IG N D Q Logic Global Routing Pool GRP

Contextual Info: Specifications ispLSI and pLSI 1048 ispLSI and pLSI 1048 ® High-Density Programmable Logic Functional Block Diagram Output Routing Pool E7 E6 E5 E4 E3 E2 E1 E0 S Output Routing Pool F7 F6 F5 F4 F3 F2 F1 F0 D Q A2 A3 A4 Logic Global Routing Pool GRP Array

20041A

Abstract: 2064VE 2064VL
Contextual Info: ispLSI 2064VL Features Functional Block Diagram • SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC • • • Input Bus Output Routing Pool ORP Input Bus A1 Logic Array B3 B2 D Q GLB B4 D Q B1 D Q D Q Input Bus Global Routing Pool (GRP) A0 A2 B5 Output Routing Pool (ORP)