Untitled
Abstract: No abstract text available
Text: Freescale Semiconductor Application Note Document Number:AN4745 Rev 0, 05/2013 Optimizing Performance on Kinetis K-series MCUs by: Melissa Hunter Contents 1 Introduction 1 In embedded systems, resources are often limited and getting
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AN4745
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AN3060
Abstract: 0x30014-0x30017 SC1400 crossbar switch 0x0000C-0x0000F 0x20000-0x20003 0x00008-0x0000B
Text: Freescale Semiconductor Application Note Document Number: AN3060 Rev. 0, 01/2006 MSC711x Optimization Techniques by Barbara Johnson Digital Systems Division Freescale Semiconductor, Inc. Austin, TX This application note discusses methods to optimize the performance of an MSC711x application. It provides
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AN3060
MSC711x
MSC711x,
SC1400
AN3060
0x30014-0x30017
crossbar switch
0x0000C-0x0000F
0x20000-0x20003
0x00008-0x0000B
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brq ti
Abstract: BRQ TI 7C
Text: D National November 1995 Semiconductor </> co 00 •Nl cn DS3875 Futurebus+ Arbitration Controller General Description The DS3875 Futurebus+ Arbitration Controller is a member of National Semiconductor’s Futurebus+ chip set designed specifically for the IEEE 896.1 Futurebus+ standard. The
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DS3875
DS3885
DS3884A
bS0112t.
D074b53
brq ti
BRQ TI 7C
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M9615
Abstract: round robin bus arbitration CRC-10 PM7375 931127
Text: PMC-Sierra, Inc. ERRATA PMC—960529R4 ISSUE 4 PM7375 LASAR-155 SATURN USER NETWORK INTERFACE PM7375 Revision F Device Errata Issue 4: December, 1997 PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 415-6000 PMC-Sierra, Inc. ERRATA
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PMC--960529R4
PM7375
LASAR-155
PM7375
M9615
round robin bus arbitration
CRC-10
931127
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GT-32090
Abstract: AD2699 PCMCIA SRAM Card MON960 QS3257 ad2690
Text: System Controller Galileo For i960JX Processors Technology, Inc. GT- 32090 Preliminary, Rev. 2.0 March 1996 NOTE: Always contact Galileo Technology for possible updates before starting a design. FEATURES • Integrated system controller for embedded applications
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i960JX
16-33MHz
128MByte
256K-4M
32-bit
20MHz
25MHz
GT-32090
AD2699
PCMCIA SRAM Card
MON960
QS3257
ad2690
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Untitled
Abstract: No abstract text available
Text: M H I H Galileo "SmsI Technology, Inc. » System Controller GT- 32090 For ¡960JX Processors _ , . _ Preliminary, Rev. 2.0 FEATURES Integrated system controller for embedded applica tions Supports the ¡960JX family of CPUs 16-33MHz bus frequency Flexible DRAM controller
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960JX
16-33MHz
128MByte
256K-4M
32-bit
20MHz
25MHz
33MHz
GT-32090
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Untitled
Abstract: No abstract text available
Text: Openbus I/F Components - VMEbus User Manual 2.0 2.1 ACC Description Introduction This section describes the AVICS Comrol Circuit ACC . A general architectural description of the ACC is provided, followed by detailed descriptions of the signal pins and major ACC functional modules, including
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EJTAG PROBE
Abstract: 20A4 AN-350 RC32332
Text: RC32334/RC32332 Differences Between Z and Y Revisions Application Note AN-350 By Paul Snell Notes Revision History February 1, 2002: Initial publication. Background The RC32334/RC32332 are integrated processors that combine a 32-bit MIPS instruction set architecture ISA CPU core with a number of on-chip peripherals to enable direct connection to boot memory, main
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RC32334/RC32332
AN-350
RC32334/RC32332
32-bit
RC32334
RC32332
EJTAG PROBE
20A4
AN-350
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FPGA based dma controller using vhdl
Abstract: design of dma controller using vhdl 64x18 synchronous sram PAR64 QL5064 REQ64
Text: Back QL5064 - QuickPCI ESP 66 MHz/64-bit PCI Controller with Embedded Programmable Logic and Dual Port SRAM Preliminary Data DEVICE HIGHLIGHTS Updated: 29-Dec-98 High Performance PCI Controller - 64-bit / 66 MHz Master/Target PCI Controller 75 MHz PCI Interface Supported for Embedded Systems
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QL5064
Hz/64-bit
29-Dec-98
64-bit
FPGA based dma controller using vhdl
design of dma controller using vhdl
64x18 synchronous sram
PAR64
REQ64
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RS690M
Abstract: radeon 7500 RS690 radeon igp 1012 RS690MC ATI RS690 graphics card AMD Radeon HIS RX 480 ATI Mobility Radeon g3d0 Northbridge
Text: AMD RS690 ASIC Family Register Reference Guide Technical Reference Manual Rev. 3.00o P/N: 43372_rs690_rrg_3.00o 2007 Advanced Micro Devices, Inc. Trademarks AMD, the AMD Arrow logo, AMD Athlon, ATI, Mobility, PowerPlay, CrossFire, Radeon, and combinations thereof, are trademarks of Advanced Micro Devices, Inc.
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RS690
GRA07
GRA08
SEQ00
SEQ01
SEQ02
SEQ03
SEQ04
RS690M
radeon 7500
radeon igp 1012
RS690MC
ATI RS690
graphics card AMD Radeon HIS RX 480
ATI Mobility Radeon
g3d0
Northbridge
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C6748 EDMA
Abstract: OMAP-L138 setup USB interrupts of arm9 TMDXOSKL138BET UART Program Examples ARM edma3 c6748 OMAP-L138 arm sata nand control OMAP-L138 arm9 c674x floating point dsp 32-KBL1D
Text: Texas Instruments OMAPL1x—based on ARM9 Low Power SoCs TI embedded processors ARM DSP C6000 Multi-core C64x DM644x Performance Power Cortex A8 DM646x OMAP4 OMAP35x ARM9 Cortex A8 C5000 C67x/C64x C674x C2000 MSP430 Cortex M3 ARM Core Code Compatibility ISA
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C6000
DM644x
DM646x
OMAP35x
C5000
C67x/C64x
C674x
C2000
MSP430
C6748 EDMA
OMAP-L138 setup USB
interrupts of arm9
TMDXOSKL138BET
UART Program Examples ARM
edma3 c6748
OMAP-L138
arm sata nand control
OMAP-L138 arm9 c674x floating point dsp
32-KBL1D
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VA22
Abstract: 68 pin pcb SCSI connector CPU-41 68c681 XICOR X24C16 VA23 CPU61 D-82054 RS232 8 pin MINI DIN 9 pole 82C503
Text: User’s Manual CPU61 / CPU41 4th edition Declaration of Conformity We, Manufacturer MicroSys Electronics GmbH Mühlweg 1 D-82054 Sauerlach Germany declare that the product CPU 61 / CPU 41 is in conformity with: EN 50081-1 Generic emission standard EN 50082-1 Generic immunity standard
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CPU61
CPU41
D-82054
EW178MA-01AG
CPU41AG
VA22
68 pin pcb SCSI connector
CPU-41
68c681
XICOR X24C16
VA23
RS232 8 pin MINI DIN 9 pole
82C503
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ROUND ROBIN ARBITRATION AND FIXED PRIORITY SCHEME
Abstract: RC334 0X00FF0000
Text: Software Configuration of PCI Bridge on RC32334 Integrated Processor Notes Technical Note TN-45 By Harpinder Singh Intr Introduction This technical note describes the steps requires to initialize the PCI bridge on the RC32334. Specifically, this includes some example code as to how to initialize the device to support a host mode configuration,
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RC32334
TN-45
RC32334.
32-bit
ROUND ROBIN ARBITRATION AND FIXED PRIORITY SCHEME
RC334
0X00FF0000
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BUS22 B1
Abstract: PI7C9X20404 TLP 723 PI7C9X20404GP 148-PIN IS24C04 msi 7267 ROUND ROBIN ARBITRATION AND FIXED PRIORITY SCHEME
Text: PI7C9X20404GP PCI EXPRESS PACKET SWITCH DATASHEET REVISION 1.6 June 2009 3545 North 1ST Street, San Jose, CA 95134 Telephone: 1-877-PERICOM, 1-877-737-4266 FAX: 408-435-1100 Internet: http://www.pericom.com PI7C9X20404GP 4Port-4Lane PCI Express Switch GreenPacketTM Family
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PI7C9X20404GP
1-877-PERICOM,
PI7C9X20404GPNBE
9X20404GP
148-pin
BUS22 B1
PI7C9X20404
TLP 723
PI7C9X20404GP
IS24C04
msi 7267
ROUND ROBIN ARBITRATION AND FIXED PRIORITY SCHEME
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PI7C9X20508
Abstract: PI7C9X20508GP IS24C04 rw1112 beacon transmitter Greenpacket
Text: PI7C9X20508GP PCI EXPRESS PACKET SWITCH DATASHEET REVISION 1.5 June 2009 3545 North 1ST Street, San Jose, CA 95134 Telephone: 1-877-PERICOM, 1-877-737-4266 FAX: 408-435-1100 Internet: http://www.pericom.com PI7C9X20508GP 5Port-8Lane PCI Express Switch GreenPacketTM Family
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1-877-PERICOM,
PI7C9X20508GPNDE
9X20508GP
256-pin
PI7C9X20508
PI7C9X20508GP
IS24C04
rw1112
beacon transmitter
Greenpacket
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PI7C9X20505GP
Abstract: No abstract text available
Text: PI7C9X20505GP PCI EXPRESS PACKET SWITCH CONFIDENTIAL – PRELIMINARY DATASHEET REVISION 0.8 August 2007 3545 North 1ST Street, San Jose, CA 95134 Telephone: 1-877-PERICOM, 1-877-737-4266 FAX: 408-435-1100 Internet: http://www.pericom.com PI7C9X20505GP 5Port-5Lane PCI Express Switch
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PI7C9X20505GP
MDS070004C
PI7C9X20505GPNDE
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Blackfin Processor
Abstract: EE core ADSP-BF561 EE-271 EE-301 EE-324 EE301
Text: Engineer-to-Engineer Note a EE-324 Technical notes on using Analog Devices DSPs, processors and development tools Visit our Web resources http://www.analog.com/ee-notes and http://www.analog.com/processors or e-mail processor.support@analog.com or processor.tools.support@analog.com for technical support.
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EE-324
EE-301)
EE-306)
EE-271)
EE-324)
Blackfin Processor
EE core
ADSP-BF561
EE-271
EE-301
EE-324
EE301
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0x858
Abstract: "24 pin" DRAM
Text: {[¡["¡"Galileo '•«bk Technology f î T - R d f l1 A. U ü I “T Product Preview Revision0.1 R4640 System Controller 3/12/97 Please contact Galileo Technology for possible updates before finalizing a design. FEATURES Low-cost integrated system controller for R4640,
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R4640,
R4650
50MHz
32-bits
512MB
256KB-16MB
32-bit,
64-bit
24-bit
32-bit
0x858
"24 pin" DRAM
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LA0-RD37
Abstract: No abstract text available
Text: PRELIMINARY DS3131 BoSS Bit SynchronouS HDLC Controller www.maxim-ic.com FEATURES § § § § § § 40 timing independent bit synchronous ports 40Rx and 40Tx coupled with 40 independent Bidirectional HDLC channels Each port can operate up to 52 Mbps 132Mbps full-duplex throughput
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DS3131
132Mbps
25MHz
33MHz
32-bit
DS3134
DS3131
DS3131.
LA0-RD37
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6K8k
Abstract: LTSX E3 PM7330 package marking 3LW ON
Text: PM7326 S/UNI-APEX PRELIMINARY DATASHEET PMC-981224 ISSUE 3 ATM/PACKET TRAFFIC MANAGER AND SWITCH PM7326 TM S/UNI - APEX S/UNI-APEX ATM/PACKET TRAFFIC MANAGER AND SWITCH DATA SHEET PRELIMINARY ISSUE 3: JUNE 1999 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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PMC-981224
PM7326
PMC-981224
PMC-980448
6K8k
LTSX E3
PM7330
package marking 3LW ON
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SH7615
Abstract: No abstract text available
Text: Section 1 Overview 1.1 Features of SuperH Microcomputer with On-Chip Ethernet Controller The SH7615 is a CMOS single-chip microcontroller that integrates a high-speed CPU core using an original Hitachi architecture with supporting functions required for an Ethernet system.
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ROUND ROBIN ARBITRATION AND FIXED PRIORITY
Abstract: SH7616
Text: Section 1 Overview 1.1 Features of SuperH Microcomputer with On-Chip Ethernet Controller The SH7616 is a CMOS single-chip microcontroller that integrates a high-speed CPU core using an original Hitachi architecture with supporting functions required for an Ethernet system.
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ROUND ROBIN ARBITRATION AND FIXED PRIORITY
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IDT77155
Abstract: IDT77V400 IDT77V500 IDT77V550 IDT79R36100 IDT79RV3041 IDT79RV4640 s-link
Text: SECTION 3 IDT77V500 Switch Controller 3.1 IDT77V500 Switch Controller Description The IDT77V500 manages the IDT77V400, a single device shared memory ATM switch. The IDT77V400 provides cell buffers implemented in Fusion Memory technology and, as the name implies, a data path for ATM cells. It also provides a means by which an external
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IDT77V500
IDT77V400,
IDT77V400
IDT77155
IDT77V550
IDT79R36100
IDT79RV3041
IDT79RV4640
s-link
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TP31C
Abstract: DS3131 DS3134 LA10 LA12 TD39 811B
Text: DALLAS SEMICONDUCTOR DS3131 Preliminary Data Sheet V2 January 26, 1999 DALLAS SEMICONDUCTOR DS3131 BoSS Bit SynchronouS HDLC CONTROLLER 40 Port / 40 Channel HDLC Controller with Option for Local Bus Access Preliminary Data Sheet Version 2 January 26, 1999
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DS3131
DS3131
164Mbps
132Mbps.
50MHz
33MHz.
DS3131.
TP31C
DS3134
LA10
LA12
TD39
811B
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