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    Text: PI6C2402 Phase-Locked Loop Clock Driver Features Description • 2X CLK_IN on CLK_OUT The PI6C2402 features a low-skew, low-jitter, phase-locked loop PLL clock driver. By connecting the feedback CLK_OUT output to the feedback FB_IN input, the propagation delay from the


    Original     		PDF PI6C2402 100ps PI6C2402 PI6C2402W PI6C2402WE 150-mil PS8418F