ST CHN t4
Abstract: No abstract text available
Text: QL5064 QuickPCI Data Sheet •••••• 66 MHz/64-bit PCI Master/Target with Embedded Programmable Logic and Dual Port SRAM Device Highlights High Performance PCI Controller • 64-bit/66 MHz Master/Target PCI Controller automatically backwards compatible to 33 MHz
|
Original
|
PDF
|
QL5064
Hz/64-bit
64-bit/66
32-bits)
64-bit
busses/100
ST CHN t4
|
Untitled
Abstract: No abstract text available
Text: QL5064 QuickPCI Data Sheet •••••• 66 MHz/64-bit PCI Master/Target with Embedded Programmable Logic and Dual Port SRAM Device Highlights High Performance PCI Controller • 64-bit/66 MHz Master/Target PCI Controller automatically backwards compatible to 33 MHz
|
Original
|
PDF
|
QL5064
Hz/64-bit
64-bit/66
32-bits)
64-bit
busses/100
|
Untitled
Abstract: No abstract text available
Text: QL6250 Eclipse Data Sheet • • • • • • Combining Performance, Density, and Embedded RAM Device Highlights Advanced Clock Network • Nine Global Clock Networks: Flexible Programmable Logic • .25 µm, Five layer metal CMOS Process • One Dedicated
|
Original
|
PDF
|
QL6250
304-bit
|
Untitled
Abstract: No abstract text available
Text: Eclipse II Family Data Sheet • • • • • • Ultra-Low Power FPGA Combining Performance, Density, and Embedded RAM Device Highlights Advanced Clock Network • Multiple dedicated low skew clock networks Flexible Programmable Logic • High drive input-only networks
|
Original
|
PDF
|
|
Untitled
Abstract: No abstract text available
Text: QL58x2 Enhanced QuickPCI Family Data Sheet • • • • • • 33/66 MHz/32-bit PCI Master/Target with Embedded Programmable Logic, Embedded Computational Units, and Dual Port SRAM Device Highlights Extendable PCI Functionality High Performance PCI Controller
|
Original
|
PDF
|
QL58x2
Hz/32-bit
32-bit
|
Untitled
Abstract: No abstract text available
Text: Eclipse II Family Data Sheet • • • • • • Ultra-Low Power FPGA Combining Performance, Density, and Embedded RAM Device Highlights Advanced Clock Network • Multiple dedicated low skew clock networks Flexible Programmable Logic • High drive input-only networks
|
Original
|
PDF
|
|
Untitled
Abstract: No abstract text available
Text: QL58x0 Enhanced QuickPCI Target Family Data Sheet • • • • • • 33/66 MHz/32-bit PCI Target with Embedded Programmable Logic, Embedded Computational Units, and Dual Port SRAM Device Highlights Extendable PCI Functionality High Performance PCI Controller
|
Original
|
PDF
|
QL58x0
Hz/32-bit
32-bit
95/98/2000/NT
484-ball
|
Appnote60
Abstract: No abstract text available
Text: Eclipse Family Data Sheet • • • • • • Combining Performance, Density, and Embedded RAM Device Highlights Flexible Programmable Logic • 0.25 µ, 5 layer metal CMOS process • 2.5 V Vcc, 2.5/3.3 V dive capable I/O • Up to 4032 logic cells • Up to 583,000 max system gates
|
Original
|
PDF
|
304-bit
Appnote60
|
DD 127 D TRANSISTOR
Abstract: diagrams hitachi ecu hitachi ecu datasheet PQ208 PT280 QL82SD QL82SD-PQ208 QL82SD-PS484 QL82SD-PT280 diagrams hitachi c13 ecu
Text: QL82SD Device Data Sheet •••••• Device Highlights Extended Features LVDS SERDES Basic Features The following can be implemented into the programmable logic: • 10 High Speed Bus LVDS Serial Links— • • • • • • • • • • •
|
Original
|
PDF
|
QL82SD
10-bit
DD 127 D TRANSISTOR
diagrams hitachi ecu
hitachi ecu datasheet
PQ208
PT280
QL82SD-PQ208
QL82SD-PS484
QL82SD-PT280
diagrams hitachi c13 ecu
|
asynchronous fifo vhdl
Abstract: 8 BIT ALU design with verilog/vhdl code full subtractor using ic 74138 74139 for bcd to excess 3 code vhdl code for 8bit bcd to seven segment display 32 BIT ALU design with verilog/vhdl code 74594 16 BIT ALU design with verilog/vhdl code B1516 RAM1024
Text: QuickWorks User Manual with SpDE Reference Release 2009.2.1 Contact Information QuickLogic Corporation 1277 Orleans Drive Sunnyvale, CA 94089 Phone: (408) 990-4000 (US) (905) 940-4149 (Canada) +(44) 1932-57-9011 (Europe) +(852) 2567-5441 (Asia) E-mail: info@quicklogic.com
|
Original
|
PDF
|
|
AA10
Abstract: AA13 AA15 QL6250 QL6250-4PQ208C QL6250-4PS484C QL6250-4PT280C
Text: QL6250 Eclipse Data Sheet • • • • • • Combining Performance, Density, and Embedded RAM Device Highlights Advanced Clock Network • Nine Global Clock Networks: Flexible Programmable Logic • 0.25 µm, Five layer metal CMOS Process • One Dedicated
|
Original
|
PDF
|
QL6250
304-bit
AA10
AA13
AA15
QL6250-4PQ208C
QL6250-4PS484C
QL6250-4PT280C
|
Untitled
Abstract: No abstract text available
Text: 4/ (FOLSVH( 'DWD 6KHHW 3*$ &RPELQLQJ 3HUIRUPDQFH 'HQVLW\ DQG (PEHGGHG 5$0 'HYLFH +LJKOLJKWV $GYDQFHG &ORFN 1HWZRUN Nine Global Clock Networks: )OH[LEOH 3URJUDPPDEOH /RJLF 0.18 µm six layer metal CMOS Process One Dedicated Eight Programmable
|
Original
|
PDF
|
304-bit
|
Untitled
Abstract: No abstract text available
Text: 4/ FOLSVH3OXV 'DWD 6KHHW WWWWWW &RPELQLQJ 3HUIRUPDQFH 'HQVLW\ DQG (PEHGGHG 5$0 'HYLFH +LJKOLJKWV OH[LEOH 3URJUDPPDEOH /RJLF .25 µm five layer metal CMOS Process $GYDQFHG &ORFN 1HWZRUN Nine Global Clock Networks: One Dedicated Eight Programmable
|
Original
|
PDF
|
304-bit
|
QL6250-4PQ208C
Abstract: df4g
Text: 4/ FOLSVH 'DWD 6KHHW W W W W W W &RPELQLQJ 3HUIRUPDQFH 'HQVLW\ DQG (PEHGGHG 5$0 'HYLFH +LJKOLJKWV OH[LEOH 3URJUDPPDEOH /RJLF .25 µm, Five layer metal CMOS Process $GYDQFHG &ORFN 1HWZRUN Nine Global Clock Networks: One Dedicated Eight Programmable
|
Original
|
PDF
|
304-bit
QL6250-4PQ208C
df4g
|
|
diode F6 5G
Abstract: TCO 706
Text: 4/ FOLSVH3OXV 'DWD 6KHHW WWWWWW &RPELQLQJ 3HUIRUPDQFH 'HQVLW\ DQG (PEHGGHG 5$0 'HYLFH +LJKOLJKWV OH[LEOH 3URJUDPPDEOH /RJLF .25 µm five layer metal CMOS Process $GYDQFHG &ORFN 1HWZRUN Nine Global Clock Networks: One Dedicated Eight Programmable
|
Original
|
PDF
|
304-bit
diode F6 5G
TCO 706
|
RH1034-1.2
Abstract: No abstract text available
Text: 4/ FOLSVH3OXV 'DWD 6KHHW WWWWWW &RPELQLQJ 3HUIRUPDQFH 'HQVLW\ DQG (PEHGGHG 5$0 'HYLFH +LJKOLJKWV OH[LEOH 3URJUDPPDEOH /RJLF .25 µm five layer metal CMOS Process $GYDQFHG &ORFN 1HWZRUN Nine Global Clock Networks: One Dedicated Eight Programmable
|
Original
|
PDF
|
304-bit
RH1034-1.2
|
Untitled
Abstract: No abstract text available
Text: QL6500 Eclipse Data Sheet • • • • • • Combining Performance, Density and Embedded RAM 1.0 Device Highlights Flexible Programmable Logic • .25u, 5 layer metal CMOS Process Advanced Clock Network • 9 Global Clock Networks • 2.5 V Vcc, 2.5/3.3 V Drive Capable I/O
|
Original
|
PDF
|
QL6500
304-bit
|
Untitled
Abstract: No abstract text available
Text: This document was generated on 12/16/2013 PLEASE CHECK WWW.MOLEX.COM FOR LATEST PART INFORMATION Part Number: Status: Overview: Description: 48409-0003 Active Consumer USB Products Universal Serial Bus USB 3.0 I/O Receptacle, Dual Port Stacked, Vertical , Type A,
|
Original
|
PDF
|
PS-48409-001
TS-48409-001
48409Series
SD-48409-001
|
Untitled
Abstract: No abstract text available
Text: This document was generated on 12/16/2013 PLEASE CHECK WWW.MOLEX.COM FOR LATEST PART INFORMATION Part Number: Status: Overview: Description: 48406-0004 Active Consumer USB Products Universal Serial Bus USB 3.0 I/O Receptacle, Dual Port Stacked, Right-Angle, Type
|
Original
|
PDF
|
PS-48406-001
TS-48406-001
48406Series
SD-48406-001
|
Untitled
Abstract: No abstract text available
Text: This document was generated on 12/16/2013 PLEASE CHECK WWW.MOLEX.COM FOR LATEST PART INFORMATION Part Number: Status: Overview: Description: 48408-0003 Active Consumer USB Products Universal Serial Bus USB 3.0 I/O Receptacle, Vertical , Type A, High-Temperature
|
Original
|
PDF
|
PS-48408-001
TS-48408-001
48408Series
SD-48408-001
|
PQ208
Abstract: PT280 QL6250 QL6325 QL6500 QL6600 bga 484 0.8mm pitch
Text: Eclipse Family Data Sheet Eclipse: Combining Performance, Density, and Embedded RAM Updated 8/24/2000 Eclipse Family DEVICE HIGHLIGHTS Device Highlights Flexible Programmable Logic • .25u, 5 layer metal CMOS process ■ 2.5 V Vcc, 2.5/3.3 V drive capable I/O
|
Original
|
PDF
|
PS672
PQ208
PT280
PS484
PB516
QL6250
QL6325
QL6500
QL6600
PQ208
PT280
QL6250
QL6325
QL6500
QL6600
bga 484 0.8mm pitch
|
AA10
Abstract: AA13 AA15 QL6500 QL6500-4PS484C QL6500-4PT280C THL W8 BU20
Text: QL6500 Eclipse Data Sheet • • • • • • Combining Performance, Density and Embedded RAM Device Highlights Advanced Clock Network • Nine Global Clock Networks: Flexible Programmable Logic • 0.25 µm, Five layer metal CMOS Process • One Dedicated
|
Original
|
PDF
|
QL6500
304-bit
AA10
AA13
AA15
QL6500-4PS484C
QL6500-4PT280C
THL W8
BU20
|
Untitled
Abstract: No abstract text available
Text: QL7120 QuickDSP Data Sheet • • • • • • Combining Embedded DSP Blocks, Performance, Density, and Embedded RAM 1.0 Device Highlights Clock Network High Speed Customizable Logic • 9 global clock networks • 0.25u, 5 layer metal CMOS process • 1 dedicated, 8 programmable
|
Original
|
PDF
|
QL7120
|
QL5842
Abstract: OA131 LVCMOS25 PCI32 QL5822 oa48
Text: QL58x2 Enhanced QuickPCI Family Data Sheet • • • • • • 33/66 MHz/32-bit PCI Master/Target with Embedded Programmable Logic, Embedded Computational Units, and Dual Port SRAM Device Highlights Extendable PCI Functionality High Performance PCI Controller
|
Original
|
PDF
|
QL58x2
Hz/32-bit
32-bit
QL5842
OA131
LVCMOS25
PCI32
QL5822
oa48
|