APPNOTE60 Search Results

Contextual Info: Eclipse II Family Data Sheet • • • • • • Ultra-Low Power FPGA Combining Performance, Density, and Embedded RAM Device Highlights Advanced Clock Network • Multiple dedicated low skew clock networks Flexible Programmable Logic • High drive input-only networks

Contextual Info: QL58x2 Enhanced QuickPCI Family Data Sheet • • • • • • 33/66 MHz/32-bit PCI Master/Target with Embedded Programmable Logic, Embedded Computational Units, and Dual Port SRAM Device Highlights Extendable PCI Functionality High Performance PCI Controller

Contextual Info: QuickLogic PolarPro Data Sheet • • • • • • Combining Low Power, Performance, Density, and Embedded RAM Device Highlights  4 programmable global clock networks • Quadrant-based segmentable clock networks Low Power Programmable Logic  20 quad clock networks per device

32x32 Multiplier

Contextual Info: QL903M QuickMIPS Data Sheet •••••• QuickMIPS Embedded Standard Product ESP Family Device Highlights Two Ethernet Controllers CPU Core • Two 10/100 MACs • 32-bit MIPS 4Kc processor runs up to 200 MHz (260 Dhrystone MIPS) • 1.3 Dhrystone MIPS per MHz

Contextual Info: Eclipse II Family Data Sheet • • • • • • Ultra-Low Power FPGA Combining Performance, Density, and Embedded RAM Device Highlights Advanced Clock Network • Multiple dedicated low skew clock networks Flexible Programmable Logic • High drive input-only networks

Contextual Info: QL58x0 Enhanced QuickPCI Target Family Data Sheet • • • • • • 33/66 MHz/32-bit PCI Target with Embedded Programmable Logic, Embedded Computational Units, and Dual Port SRAM Device Highlights Extendable PCI Functionality High Performance PCI Controller

Appnote60

Contextual Info: Eclipse Family Data Sheet • • • • • • Combining Performance, Density, and Embedded RAM Device Highlights Flexible Programmable Logic • 0.25 µ, 5 layer metal CMOS process • 2.5 V Vcc, 2.5/3.3 V dive capable I/O • Up to 4032 logic cells • Up to 583,000 max system gates

DS5250

Abstract: DS5230 DS80C310 DS80C320 DS80C390 DS80C400 DS87C520 DS87C530 DS89C430 DS89C450
Contextual Info: Maxim > App Notes > MICROCONTROLLERS Keywords: DS5230, DS5250, DS80C310, DS80C320, DS87C520, DS87C530, DS80C390, DS80C400, DS89C430, DS89C450, high-speed microcontroller, ultra high-speed microcontroller, UART, RS-232, serial port, dual data pointer, FIFO, example co

DS5250

Abstract: AN605 DS80C310 DS80C390 DS80C400 DS89C430 DS89C450 Delta dps delta dps-1001ab-1
Contextual Info: Maxim > App Notes > Microcontrollers Keywords: high-speed microcontroller, dual data pointers, DPTR, DS5250, DS80C390, DS80C400, DS89C430, DS89C450, DPTR, sample code, MOVX operation, Dallas Semiconductor, microcontrollers Apr 03, 2002 APPLICATION NOTE 605

QL904M

Abstract: LVCMOS25 MIPS32 PC-100 QL904M175 QL904M200 R4000
Contextual Info: QL904M QuickMIPS Data Sheet •••••• QuickMIPS Embedded Standard Product ESP Family Device Highlights Ethernet Controller CPU Core • 10/100 MAC • 32-bit MIPS 4Kc processor runs up to 200 MHz (260 Dhrystone MIPS) • 1.3 Dhrystone MIPS per MHz

Contextual Info: 4/ FOLSVH3OXV 'DWD 6KHHW WWWWWW &RPELQLQJ 3HUIRUPDQFH 'HQVLW\ DQG (PEHGGHG 5$0 'HYLFH +LJKOLJKWV OH[LEOH 3URJUDPPDEOH /RJLF ‡ .25 µm five layer metal CMOS Process $GYDQFHG &ORFN 1HWZRUN ‡ Nine Global Clock Networks: ‡ One Dedicated ‡ Eight Programmable

TFBGA196

Abstract: 110C LVCMOS25 QL8025 QL8050 QL8150 QL8250 QL8325 QL6250E OA47
Contextual Info: Eclipse II Family Data Sheet • • • • • • Ultra-Low Power FPGA Combining Performance, Density, and Embedded RAM Device Highlights Advanced Clock Network • Multiple dedicated low skew clock networks Flexible Programmable Logic • High drive input-only networks

diode F6 5G

Abstract: TCO 706
Contextual Info: 4/ FOLSVH3OXV 'DWD 6KHHW WWWWWW &RPELQLQJ 3HUIRUPDQFH 'HQVLW\ DQG (PEHGGHG 5$0 'HYLFH +LJKOLJKWV OH[LEOH 3URJUDPPDEOH /RJLF ‡ .25 µm five layer metal CMOS Process $GYDQFHG &ORFN 1HWZRUN ‡ Nine Global Clock Networks: ‡ One Dedicated ‡ Eight Programmable

RH1034-1.2

Contextual Info: 4/ FOLSVH3OXV 'DWD 6KHHW WWWWWW &RPELQLQJ 3HUIRUPDQFH 'HQVLW\ DQG (PEHGGHG 5$0 'HYLFH +LJKOLJKWV OH[LEOH 3URJUDPPDEOH /RJLF ‡ .25 µm five layer metal CMOS Process $GYDQFHG &ORFN 1HWZRUN ‡ Nine Global Clock Networks: ‡ One Dedicated ‡ Eight Programmable

QL5842

Abstract: OA131 LVCMOS25 PCI32 QL5822 oa48
Contextual Info: QL58x2 Enhanced QuickPCI Family Data Sheet • • • • • • 33/66 MHz/32-bit PCI Master/Target with Embedded Programmable Logic, Embedded Computational Units, and Dual Port SRAM Device Highlights Extendable PCI Functionality High Performance PCI Controller

Eclipse II Family

Contextual Info: Eclipse II Family Data Sheet • • • • • • Ultra-Low Power FPGA Combining Performance, Density, and Embedded RAM Device Highlights Advanced Clock Network • Multiple dedicated low skew clock networks Flexible Programmable Logic • High drive input-only networks

Contextual Info: QuickLogic PolarPro Data Sheet • • • • • • Combining Low Power, Performance, Density, and Embedded RAM Device Highlights • Quadrant-based segmentable clock networks  20 quad clock networks per device Flexible Programmable Logic  4 quad clock networks per quadrant

mips r4000

Contextual Info: QL902M QuickMIPS Data Sheet •••••• QuickMIPS Embedded Standard Product ESP Family Device Highlights Two Ethernet Controllers CPU Core • Two 10/100 MACs • 32-bit MIPS 4Kc processor runs up to 200 MHz (260 Dhrystone MIPS) • 1.3 Dhrystone MIPS per MHz

Contextual Info: Eclipse Family Data Sheet • • • • • • Combining Performance, Density, and Embedded RAM Device Highlights Flexible Programmable Logic • 0.25 µm, 5 layer metal CMOS process • 2.5 V Vcc, 2.5/3.3 V dive capable I/O • Up to 4032 logic cells • Up to 583,000 max system gates

Contextual Info: QuickLogic PolarPro Data Sheet • • • • • • Combining Low Power, Performance, Density, and Embedded RAM • Quadrant-based segmentable clock networks Device Highlights Flexible Programmable Logic • 0.18 µm, six layer metal CMOS process • 1.8 V core voltage, 1.8/2.5/3.3 V drive

ECU schematic diagram

Contextual Info: QL6250E Eclipse-E Data Sheet •••••• FPGA Combining Performance, Density, and Embedded RAM Device Highlights Advanced Clock Network • Nine global clock networks: Flexible Programmable Logic  One dedicated • 0.18 µm six layer metal CMOS process

Contextual Info: Eclipse-II Family Data Sheet • • • • • • Ultra-Low Power FPGA Combining Performance, Density, and Embedded RAM Device Highlights Advanced Clock Network • Multiple dedicated low skew clock networks Flexible Programmable Logic • High drive input-only networks

1024X3

Contextual Info: QL903M QuickMIPS Data Sheet •••••• QuickMIPS Embedded Standard Product ESP Family Device Highlights Two Ethernet Controllers CPU Core • Two 10/100 MACs • 32-bit MIPS 4Kc processor runs up to 200 MHz (260 Dhrystone MIPS) • 1.3 Dhrystone MIPS per MHz

QL58x2

Contextual Info: QL58x2 Enhanced QuickPCI Family Data Sheet • • • • • • 33/66 MHz/32-bit PCI Master/Target with Embedded Programmable Logic, Embedded Computational Units, and Dual Port SRAM Device Highlights High Performance PCI Controller • 33/66 MHz 32-bit PCI Master/Target