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    si4812b

    Abstract: SIC403 VJ0603Y104KXAC SiC403CD-T1-GE3 SIC401
    Text: SiC403 Vishay Siliconix microBUCK SiC403 6 A, 28 V Integrated Buck Regulator with Programmable LDO DESCRIPTION FEATURES The Vishay Siliconix SiC403 is an advanced stand-alone synchronous buck regulator featuring integrated power MOSFETs, bootstrap switch, and a programmable LDO in a


    Original     		SiC403 SiC403 2011/65/EU 2002/95/EC. 2002/95/EC 2011/65/EU. 12-Mar-12 si4812b VJ0603Y104KXAC SiC403CD-T1-GE3 SIC401 PDF

    bzx 850

    Abstract: bzx 850 30
    Text: CY7C1412AV18 CY7C1414AV18 36 Mbit QDR II SRAM Two Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth ■ 2-word burst on all accesses


    Original     		CY7C1412AV18 CY7C1414AV18 CY7C1412AV18, CY7C1414AV18 bzx 850 bzx 850 30 PDF

    Untitled

    Abstract: No abstract text available
    Text: THIS SPEC IS OBSOLETE Spec No: 001-06981 Spec Title: CY7C1523AV18/CY7C1524AV18, 72-MBIT DDR II SIO SRAM 2-WORD BURST ARCHITECTURE Sunset Owner: Jayasree Nayar NJY Replaced by: None CY7C1523AV18 CY7C1524AV18 72-Mbit DDR II SIO SRAM 2-Word Burst Architecture


    Original     		CY7C1523AV18/CY7C1524AV18, 72-MBIT CY7C1523AV18 CY7C1524AV18 CY7C1524AV18 PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1413JV18 CY7C1415JV18 36-Mbit QDR II SRAM 4-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1413JV18 – 2M x 18 ■ 300-MHz clock for high bandwidth ■ 4-word burst for reducing address bus frequency


    Original     		CY7C1413JV18 CY7C1415JV18 36-Mbit CY7C1413JV18 300-MHz PDF

    CY7C1411BV18

    Abstract: CY7C1413BV18 CY7C1415BV18 CY7C1426BV18
    Text: CY7C1411BV18, CY7C1426BV18 CY7C1413BV18, CY7C1415BV18 36-Mbit QDR -II SRAM 4-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz clock for high bandwidth ■


    Original     		CY7C1411BV18, CY7C1426BV18 CY7C1413BV18, CY7C1415BV18 36-Mbit CY7C1411BV18 CY7C1413BV18 CY7C1411BV18 CY7C1413BV18 CY7C1415BV18 CY7C1426BV18 PDF

    CY7C1510AV18

    Abstract: CY7C1512AV18 CY7C1514AV18 CY7C1525AV18 CY7C1512AV18-167BZXC
    Text: CY7C1510AV18, CY7C1525AV18 CY7C1512AV18, CY7C1514AV18 72-Mbit QDR -II SRAM 2-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1510AV18 – 8M x 8 ■ 250 MHz clock for high bandwidth


    Original     		CY7C1510AV18, CY7C1525AV18 CY7C1512AV18, CY7C1514AV18 72-Mbit CY7C1510AV18 CY7C1512AV18 CY7C1510AV18 CY7C1512AV18 CY7C1514AV18 CY7C1525AV18 CY7C1512AV18-167BZXC PDF

    CY7C1422AV18

    Abstract: CY7C1423AV18 CY7C1424AV18 CY7C1429AV18
    Text: CY7C1422AV18, CY7C1429AV18 CY7C1423AV18, CY7C1424AV18 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features Functional Description • 36-Mbit density 4M x 8, 4M x 9, 2M x 18, 1M x 36 ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency


    Original     		CY7C1422AV18, CY7C1429AV18 CY7C1423AV18, CY7C1424AV18 36-Mbit CY7C1422AV18 CY7C1423AV18 CY7C1424AV18 CY7C1429AV18 PDF

    CY7C1311CV18

    Abstract: CY7C1313CV18 CY7C1315CV18 CY7C1911CV18
    Text: CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz clock for high bandwidth ■


    Original     		CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 18-Mbit CY7C1311CV18 CY7C1313CV18 CY7C1311CV18 CY7C1313CV18 CY7C1315CV18 CY7C1911CV18 PDF

    05564

    Abstract: CY7C1522V18 CY7C1523V18 CY7C1524V18 CY7C1529V18
    Text: CY7C1522V18, CY7C1529V18 CY7C1523V18, CY7C1524V18 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features Functional Description • 72-Mbit density 8M x 8, 8M x 9, 4M x 18, 2M x 36 ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency


    Original     		CY7C1522V18, CY7C1529V18 CY7C1523V18, CY7C1524V18 72-Mbit 05564 CY7C1522V18 CY7C1523V18 CY7C1524V18 CY7C1529V18 PDF

    CY7C1520V18-200BZXC

    Abstract: CY7C1520V18-300BZC CY7C1518V18-300BZC CY7C1516V18 CY7C1518V18 CY7C1520V18 CY7C1527V18
    Text: CY7C1516V18, CY7C1527V18 CY7C1518V18, CY7C1520V18 72-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 72-Mbit density 8M x 8, 8M x 9, 4M x 18, 2M x 36 ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency


    Original     		CY7C1516V18, CY7C1527V18 CY7C1518V18, CY7C1520V18 72-Mbit CY7C1520V18-200BZXC CY7C1520V18-300BZC CY7C1518V18-300BZC CY7C1516V18 CY7C1518V18 CY7C1520V18 CY7C1527V18 PDF

    CY7C1512V18-250BZXC

    Abstract: CY7C1510V18 CY7C1512V18 CY7C1514V18 CY7C1525V18
    Text: CY7C1510V18, CY7C1525V18 CY7C1512V18, CY7C1514V18 72-Mbit QDR -II SRAM 2-Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth


    Original     		CY7C1510V18, CY7C1525V18 CY7C1512V18, CY7C1514V18 72-Mbit CY7C1512V18-250BZXC CY7C1510V18 CY7C1512V18 CY7C1514V18 CY7C1525V18 PDF

    Untitled

    Abstract: No abstract text available
    Text: THIS SPEC IS OBSOLETE Spec No: 001-12557 Spec Title: CY7C1413JV18/CY7C1415JV18, 36-MBIT QDR R II SRAM 4-WORD BURST ARCHITECTURE Sunset Owner: Jayasree Nayar (NJY) Replaced by: NONE CY7C1413JV18 CY7C1415JV18 36-Mbit QDR II SRAM 4-Word Burst Architecture


    Original     		CY7C1413JV18/CY7C1415JV18, 36-MBIT CY7C1413JV18 CY7C1415JV18 300-MHz PDF

    CY7C1515JV18-167BZI

    Abstract: No abstract text available
    Text: CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 72-Mbit QDR -II SRAM 4-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1511JV18 – 8M x 8 ■ 300 MHz clock for high bandwidth


    Original     		CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 72-Mbit CY7C1511JV18 CY7C1526JV18 CY7C1513JV18 CY7C1515JV18-167BZI PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1422JV18, CY7C1429JV18 CY7C1423JV18, CY7C1424JV18 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features Functional Description • 36 Mbit density 4M x 8, 4M x 9, 2M x 18, 1M x 36 ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency


    Original     		CY7C1422JV18, CY7C1429JV18 CY7C1423JV18, CY7C1424JV18 36-Mbit CY7C1429JV18, CY7C1424JV18 PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1510JV18, CY7C1525JV18 CY7C1512JV18, CY7C1514JV18 72-Mbit QDR -II SRAM 2-Word Burst Architecture Features Configurations • Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions ■ 267 MHz Clock for High Bandwidth ■


    Original     		CY7C1510JV18, CY7C1525JV18 CY7C1512JV18, CY7C1514JV18 72-Mbit CY7C1510JV18 CY7C1525JV18 CY7C1512JV18 PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1412AV18 CY7C1414AV18 36 Mbit QDR II SRAM Two Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth ■ 2-word burst on all accesses


    Original     		CY7C1412AV18 CY7C1414AV18 CY7C1412AV18, CY7C1414AV18 PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1418AV18 CY7C1420AV18 36 Mbit DDR II SRAM Two Word Burst Architecture Features Functional Description • 36 Mbit density 2M x 18, 1M x 36 ■ 300 MHz clock for high bandwidth ■ Two word burst for reducing address bus frequency ■ Double Data Rate (DDR) interfaces 


    Original     		CY7C1418AV18 CY7C1420AV18 CY7C1418AV18, CY7C1420AV18 CY7C1420AV18, PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1422AV18, CY7C1429AV18 CY7C1423AV18, CY7C1424AV18 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features Functional Description • 36-Mbit density 4M x 8, 4M × 9, 2M × 18, 1M × 36 ■ 300 MHz clock for high bandwidth


    Original     		CY7C1422AV18, CY7C1429AV18 CY7C1423AV18, CY7C1424AV18 36-Mbit CY7C1429AV18, CY7C1424AV18 PDF

    C2512

    Abstract: No abstract text available
    Text: SiC417 Vishay Siliconix microBUCKTM SiC417 10-A, 28-V Integrated Buck Regulator with Programmable LDO DESCRIPTION FEATURES The Vishay Siliconix SiC417 is an advanced stand-alone synchronous buck regulator featuring integrated power MOSFETs, bootstrap diode, and a programmable LDO in a


    Original     		SiC417 SiC417 11-Mar-11 C2512 PDF

    GMK212B7105K

    Abstract: No abstract text available
    Text: SiC414 Vishay Siliconix microBUCKTM SiC414 6 A, 28 V Integrated Buck Regulator with 5 V LDO DESCRIPTION FEATURES The Vishay Siliconix SiC414 is an advanced stand-alone synchronous buck regulator featuring integrated power MOSFETs, bootstrap switch, and an internal 5 V LDO in a


    Original     		SiC414 SiC414 11-Mar-11 GMK212B7105K PDF

    Untitled

    Abstract: No abstract text available
    Text: SiC414 Vishay Siliconix microBUCKTM SiC414 6 A, 28 V Integrated Buck Regulator with 5 V LDO DESCRIPTION FEATURES The Vishay Siliconix SiC414 is an advanced stand-alone synchronous buck regulator featuring integrated power MOSFETs, bootstrap diode, and an internal 5 V LDO in a


    Original     		SiC414 SiC414 18-Jul-08 PDF

    CRCW04020000ZOED

    Abstract: 8834 a mosfet so-8 EU-FM1V151 MOSFET MARK H1 SM0402 vishay 8834 diode vishay P11 1R01 Si4812BDY e23l
    Text: SiC414 Vishay Siliconix microBUCKTM SiC414 6 A, 28 V Integrated Buck Regulator with 5 V LDO DESCRIPTION FEATURES The Vishay Siliconix SiC414 is an advanced stand-alone synchronous buck regulator featuring integrated power MOSFETs, bootstrap switch, and an internal 5 V LDO in a


    Original     		SiC414 SiC414 18-Jul-08 CRCW04020000ZOED 8834 a mosfet so-8 EU-FM1V151 MOSFET MARK H1 SM0402 vishay 8834 diode vishay P11 1R01 Si4812BDY e23l PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1418BV18 CY7C1420BV18 36-Mbit DDR II SRAM 2-Word Burst Architecture Features Functional Description • 36-Mbit Density 2M x 18, 1M x 36 ■ 267 MHz Clock for high Bandwidth ■ 2-word Burst for reducing Address Bus Frequency ■ Double Data Rate (DDR) Interfaces 


    Original     		CY7C1418BV18 CY7C1420BV18 36-Mbit CY7C1418BV18, CY7C1420BV18 CY7C1420BV18, 18-bit PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1310JV18, CY7C1910JV18 CY7C1312JV18, CY7C1314JV18 18 Mbit QDR -II SRAM 2-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1310JV18 – 2M x 8 CY7C1910JV18 – 2M x 9


    Original     		CY7C1310JV18, CY7C1910JV18 CY7C1312JV18, CY7C1314JV18 CY7C1310JV18 CY7C1312JV18 PDF