POWER GRID CONTROL THROUGH PC Search Results

8kx1 RAM

Contextual Info: Delta39K ISR™ CPLD Family PRELIMINARY CPLDs at FPGA Densities™ Features • Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+ • Compatible with NOBL™, ZBT™, and QDR™ SRAMs

NT208

Abstract: 1kx8 rom 250NTC
Contextual Info: Delta39K ISR™ CPLD Family PRELIMINARY CPLDs at FPGA Densities™ •Carry-chain logic for fast and efficient arithmetic operations •Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+

CY39200V

Contextual Info: Delta39K ISR™ CPLD Family PRELIMINARY CPLDs at FPGA Densities™ •Multiple I/O standards supported — LVCMOS, LVTTL, 3.3V PCI, SSTL2 I-II , SSTL3 (I-II), HSTL (I-IV), and GTL+ •Compatible with NOBL™, ZBT™, and QDR™ SRAMs •Programmable slew rate control on each I/O pin

39k200

Abstract: CY39200V
Contextual Info: Delta39K ISR™ CPLD Family PRELIMINARY CPLDs at FPGA Densities™ Features •Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+ •Compatible with NOBL™, ZBT™, and QDR™ SRAMs

CY39100V484-125BBI

Abstract: "Single-Port RAM" delta39k
Contextual Info: Delta39K ISR™ CPLD Family PRELIMINARY CPLDs at FPGA Densities™ •Multiple I/O standards supported — LVCMOS, LVTTL, 3.3V PCI, SSTL2 I-II , SSTL3 (I-II), HSTL (I-IV), and GTL+ •Compatible with NOBL™, ZBT™, and QDR™ SRAMs •Programmable slew rate control on each I/O pin

delta39k

Abstract: 39K100 39K165 39K30 39K50 CY3LV010 CY39200V
Contextual Info: Delta39K ISR™ CPLD Family PRELIMINARY CPLDs at FPGA Densities™ Features • Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+ • Compatible with NOBL™, ZBT™, and QDR™ SRAMs

39K100

Abstract: 39K30 39K50
Contextual Info: Delta39K ISR™ CPLD Family PRELIMINARY CPLDs at FPGA Densities™ Features — Clock polarity control at each register • Carry-chain logic for fast and efficient arithmetic operations • Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2

delta39k

Abstract: 39K100 39K30 39K50
Contextual Info: Delta39K ISR™ CPLD Family CPLDs at FPGA Densities™ Features • Carry-chain logic for fast and efficient arithmetic operations • Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+

Contextual Info: Delta39K ISR™ CPLD Family CPLDs at FPGA Densities™ Features • Carry-chain logic for fast and efficient arithmetic operations • Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+

CY39100V484B-125BBI

Abstract: programmable slew rate control IO AT17LV010-10JI CY39030V256-125MBC IO1 5V 39K100 39K165 39K30 39K50 CY39100V208B-125NTC
Contextual Info: Delta39K ISR™ CPLD Family CPLDs at FPGA Densities™ Features • Carry-chain logic for fast and efficient arithmetic operations • Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+

84 FBGA

Abstract: 39K100 39K200 39K30 39K50 388-BGA
Contextual Info: Delta39K ISR™ CPLD Family CPLDs at FPGA Densities™ Features • Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+ • Compatible with NOBL™, ZBT™, and QDR™ SRAMs

bga 484 0.8mm pitch

Abstract: 20532 tqfp 39K100 39K200 39K30 39K50 484FBGA CY39200V208-181NTXC CY39100V208B-125NTxC cy39030v208-125ntxc
Contextual Info: Delta39K ISR™ CPLD Family CPLDs at FPGA Densities™ Features • Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+ • Compatible with NOBL™, ZBT™, and QDR™ SRAMs

PROTOBOARD

Abstract: 8200-1010 PCIAX564
Contextual Info: Prototyping General Purpose Boards, BUS Specific Boards and Extender Cards T w i n Industries Prototyping General Purpose Boards 3 Twin Industries general purpose prototype boards provide a versatile solution for many research and development projects. Available In Four Different Types: perf board with non-plated holes, the 7100 series; perf board with plated

PROTOBOARD

Abstract: TW-E40-510 710045 8300SB1 TW-E41-102B TW-E41-1060
Contextual Info: 2083-2012.qxp:QuarkCatalogTempNew 9/20/12 4:17 PM Page 2083 28 Prototyping General-Purpose Boards and BUS Specific Boards, and Solderless Breadboards TEST & MEASUREMENT Prototyping General-Purpose Boards 7100-062 Series Non-Plated Holes 7100 Series Non-Plated Holes

CERAMIC QUAD FLATPACK CQFP 96

Contextual Info: Standard Products RadHard Eclipse FPGA Advanced Data Sheet September, 2004 www.aeroflex.com/RadHardFPGA ‰ Comprehensive design tools include high quality Verilog/ VHDL synthesis and simulation ‰ QuickLogic IP available for microcontrollers, DRAM controllers, USART and PCI

MAX11068

Abstract: GRM188R72A103KA GRM21BR71C335K ju114 MAX11080 D114 ev MAX11068EVMINIQU C101 CMZ5928B C127
Contextual Info: 19-5100; Rev 1; 10/10 MAX11068 Evaluation System The MAX11068 evaluation kit EV kit demonstrates the capabilities of the MAX11068 advanced smart batterypack controller. The EV kit PCB is made up of two boards, each containing nearly identical MAX11068 circuits. The left side of the EV kit is referenced as side

AN10897

Abstract: ES-3U5T-1B257-AA basics of wiring harness BV 3145 crystal washing machine service manual AA Class NXP antenna design guide emc design prtr5v0 EMC Guide for Printed Circuit Board 2002 Ford BAV99
Contextual Info: AN10897 A guide to designing for ESD and EMC Rev. 02 — 19 January 2010 Application note Document information Info Content Keywords ESD, EMC, PCB design Abstract An introductory approach to designing for ESD. Understanding the ESD pulse, how passive components react over frequency, and PCB layout

Contextual Info: Standard Products RadHard Eclipse FPGA Advanced Data Sheet September, 2004 www.aeroflex.com/RadHardFPGA ‰ Comprehensive design tools include high quality Verilog/ VHDL synthesis and simulation ‰ QuickLogic IP available for microcontrollers, DRAM controllers, USART and PCI

transistor et 454

Abstract: ACTEL proASIC PLUS APA450 APA300 cmos XOR Gates APA1000 APA150 APA450 APA600 APA750 ProASICPLUS v2
Contextual Info: Product Brief ProASICPLUS Family Flash FPGAs Fe a t ur es an d B e ne f i ts I/O High C apaci t y • Schmitt Trigger Option on Every Input • Mixed 2.5V/3.3V Support with Individually-Selectable Voltage and Slew Rate • Bidirectional Global I/Os • Compliance with PCI Specification Revision 2.2

Contextual Info: Standard Products RadHard Eclipse FPGA Advanced Data Sheet November, 2004 www.aeroflex.com/RadHardFPGA ‰ Comprehensive design tools include high quality Verilog/ VHDL synthesis and simulation ‰ QuickLogic IP available for microcontrollers, DRAM controllers, USART and PCI

ericsson rnv connector

Abstract: ericsson rnv sofix connector sofix connector ericsson ERICSSON
Contextual Info: Female Right-Angle Solder-to-Board 4-rows Power Connectors r ♦ ♦ ♦ ♦ ♦ For use on daughtercard to backplane/mothercard Mounting on the PCB with Hot Riveting Coding parts fit into the housing 2 performance classes; Telecom and IEC PL2 Variants for different PCB thickness

J-STD-013

Abstract: AP-399 pad DIAGRAM for RJ45 on pc board Pulse bob smith termination electrical fast transient testing 82559 printed circuit board AD30 H1012 A5829-01 82559based
Contextual Info: 82559 Printed Circuit Board PCB Design Application Note (AP-399) Revision 1.0 January 1999 Order Number: 739073-001 Revision History Revision Date Revision Description Jan. 1999 1.0 First Release Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual

2.5 MVA transformer

Contextual Info: SMA Solar Technology AG Solar Inverters MLX Series Design Guide www.SMA.de Contents Contents 1 Introduction 3 1.1 Introduction 3 1.2 List of Abbreviations 3 2 Inverter Overview 5 2.1 Product Label 5 2.2 Mechanical Overview of the Inverter 5 2.3 Description of the Inverter

20HU

Abstract: NEC VFD Display 300-pF TP6317 vfd display nec 36 pin 7 segment vfd display vfd circuit diagram 16 segment driver 06HL 12 pin 4digit 7 segment display
Contextual Info: TP6317 1/4 TO 1/11-DUTY VFD CONTROLLER/DRIVER General Description Features The TP6317 is a VFD Vacuum Fluorescent Display Multiple display modes (11-segment & 11-digit to controller/driver that is driven on a 1/4 to 1/11-duty 16-segment & 4-digit) factor. It consists of 11 segment output lines, 6 grid