PIN DIAGRAM I PROCESSOR Search Results

CL-CD2431

Contextual Info: CL-CD2431 . _ CIRRUS LOGIC 1. PIN INFORMATION 1.1 Pin Diagram — CL-CD2431 - i 'I 'i 'o ï / R X C IN [3]-► TXCIN[3] — » DSR‘ [0] — » CTS*[0] — ► TXCOUT/DTR*[OJ RTS*[0] DSR*[1] — ►

intel 8289

Abstract: interfacing 8289 with 8086 8288 bus controller interfacing with 8086 8289 bus arbiter 8086 8289 8289 bus arbiter pin of microprocessor 80386 8088 intel microprocessor pin diagram pin configuration of 8289 interfacing of 8289 with 8086 microprocessor
Contextual Info: one M BI8289A/8289B MULTIBUS R I iAPX 86/88/186 Bus Arbiter January 1989 Distinctive Features- General Descriptioru Emulates Intel 8289 Bus Arbiter, however, not pin for pin compatible. Please refer to pinout diagram. Provides arbitration o f m ultiple masters on MULTIBUS I.

D2400

Abstract: CD2401 CL-CD2401
Contextual Info: CL-CD2400/ CD2401 M ulti-Protocol Com m unications Controller CIRRUS LOGIC PIN INFORMATION Pin Diagram — CL-CD2400 = •& l l i i i i / CTS' O H TXCOUT/DTR*[0] C r t s *[o] r CTS‘ [1 ]C TXCOUT/DTR*[1 ] C RTS* [1 C GND C CTS‘ [2] L TXCOUT/DTR*[2] C RTS'[2) □

Intel 8289

Abstract: priority logic using 8289
Contextual Info: M B I 8 2 8 9 A /8 2 8 9 B MULTIBUS I iAPX 86/88/186 Bus Arbiter Distinctive Features_ • Emulates Intel 8289 Bus Arbiter, however, not pin tor pin compatible. Please refer to pinout diagram. • Provides arbitration o f m ultiple masters on

MQUAD

Abstract: 1110E GA1086 GA1086-MC1000 GA1086-MC500 MC500 avw 13
Contextual Info: T R I Q U I N T S E M I C O N D U C T O R , I N C 7Q gt GA1086 Figure 1. Block Diagram 11-Output dock Buffer Features • Operates from 30 MHz to 67MHz • Pin-to-pin output skew of 250 ps max • Period-to-period jitter: 75 ps (typ) microprocessors, with near zero input-to-output delay and very low pin-to-

intel 8289

Contextual Info: J Q D L ^ MBI 8289A/8289B ^ •a ^ T S rT T T ^ MULTIBUS R I iAPX 86/88/186 Bus Arbiter January 1989 Distinctive Features- General Description. Emuiates Intel 8289 Bus Arbiter, however, not pin for pin compatible. Please refer to pinout diagram. Provides arbitration of multiple masters on MULTIBUS I.

Contextual Info: T R I COMPUTING Q U AND I N T S E M I C O N D U C T O R , NETWORKING Figure 1. Block Diagram FBIN S1 I N C C LK SO NC NC GA1086 GND Features I • Operates from 30 MHz to 67 MHz ■ ■ Pin-to-pin output skew o f 2 5 0 ps max ■ Period-to-period jitter: 75 ps (typ)

Contextual Info: & CROCH.P P I C 1 6 C 7 1 / 7 7 7 / 7 7 1 18/20-Pin, 8-Bit CMOS Microcontrollers with 10/12-Bit A/D Microcontroller Core Features: Pin Diagram • High-performance RISC CPU 20-Pin PDIP, SOIC, SSOP • Only 35 single word instructions to learn R A 0 /A N 0 -W

MSVR

Contextual Info: CL-CD2481 Programmable Communications Controller FCIRRUS LOGIC PIN INFORMATION Pin Diagram — CL-CD2481 î g n £ s ß e s a e e e g s s s s s s a .•□nnnnnnnnnnnnnnnnnnn / RXCIN[3] ~ TXCIN[3] d DSR*[0]C C T S *[0 ][I TXCOUT/DTB*[0]C RTS“[0] C D S R *[1][I

TriQuint

Contextual Info: T fl ! COMPUTING I AND ! T S E M I C O N D U C T O R , NETWORKING Figure 1. Block Diagram FBIN S1 I N C C LK SO NC NC GND GA1086 11-Output Data Sheets Clock Buffer Features • Operates from 30 MHz to 67 MHz • Pin-to-pin output skew o f 250 ps max) • Period-to-period jitter: 75 ps (typ)

BA1000

Abstract: U902 gal 504 GA1086 GA1086-MC500 MC500
Contextual Info: f H / Q U l fi r\ S E M I C O N D U C T O R , I N C T O S I COMPUTING AND NETWORKING Figure 1. Block Diagram FBIN S1 CLK SO NC NC GA1086 GND VDD Q9 11-Output Clock Buffer Q8 GND Features \ Q7 * Operates from 30 MHz to 67 MHz '• Q6 a Pin-to-pin output skew of

AD3860

Abstract: PIA 8255 8255 PIA pin diagram
Contextual Info: ,. W Complete, VoltageOutput 12-BitBufferedOAC ANALOG DEVICES AD3860.1 I AD3860 FUNCTIONAL FEATURES Resolution: 12 Bits BLOCK DIAGRAM '"""0'." Nonlinearity: j: 1/2LSBTmlnto Tmex "', ~ 1t: 12-Bit Input Register Small Size: 24 pin DIP Fast Settling: 5fLSto j:O.O1%

Contextual Info: S E M I C C N D U C T O R I N C :i: Figure 1. Block Diagram FBIN S1 CLK SO NC NC GND GA1086 11-Output Clock Buffer Features * Operates from 30 MHz to 67 MHz * Pin-to-pin output skew o f 2 5 0 ps max TriQuint’s GA1086 operates from 30 MHz to 67 MHz. This TTL-level clock buffer chip

74AS04

Abstract: 74AS32 HSP48410 TB305 TMS320 TMS320C25
Contextual Info: Histogramming With A Variable Pixel Increment Technical Brief April 1998 TB305.1 Introduction RAM IN OUT ADDRESS S DIO DIO 0-23 I/F DIN 0-23 START ADDRESS GENERATOR MUX PIN 0-9 REG “0” RD “1” PIN 0-9 START CONTROL FIGURE 1. HISTOGRAMMER MODE BLOCK DIAGRAM

Contextual Info: T R I 7 Q Q U I N T S E M I C O N D U C T O R , I N C Ö Figure 1. Block Diagram FBIN GA1086 S1 C LK SO NC NC GND 11-Output Clock Buffer Features • Operates from 30 MHz to 67 MHz • Pin-to-pin output skew of 250 p s max • TriQuint’s GA1086 operates from 30 MHz to 67 MHz. This TTL-level clock

automotive ecu manual

Abstract: DATASHEET OF LED 55B JP391 JS28F320 microblaze ethernet pd26 sma automotive ecu circuit automotive ecu spartan 3a u660
Contextual Info: XA1600E Development Board Reference Manual Contents 2 3 Introduction Block Diagram of the XA1600E Package contents Getting started 6 Overview XA1600E User interface XA1600E LED’s, buttons, & jumpers 11 Pin out descriptions X300: Communication connector J500: I/O extension connector

ga1000

Contextual Info: s CO M PU TIN G AND e m I c o n D U S1 T 0 R , I N C NETW ORKING Figure 1. Block Diagram FBIN C C LK SO NC NC GN D GA1086 11-Output Clock Buffer Features * Operates from 30 MHz to 67 MHz a Pin-to-pin output skew of 250ps max * Period-to-period jitter: 75 ps (typ)

max8736a

Abstract: G966-25 ICS9PR363BGLF 8C540 G96625ADJF1UF A23 851-1 diode BE25 quanta computer max1993etg quanta
Contextual Info: 1 2 3 4 5 1 PB3 Block Diagram VRAM CPU Merom VRAM GDDR2 GDDR2 128M/ 256M A 478 PIN micro FC-PGA B-Channel 500MHZ LCD TMDS DVI-I Digital & Analog 14.318MHz TMDS P21 CLOCK GEN P10 965GM/PM PCIE 16Lanes ICS9PR363BGLF P2 1299 PIN (micro FCBGA) 35mm x 35mm HDMI

TS189

Contextual Info: M i c r o c h PIC17C4X i p High-Performance 8-Bit CMOS EPROM/ROM Microcontroller Pin Diagram Devices included in this data sheet: • PIC17CR42 PDIP, CERDIP, Windowed CERDIP • PIC17C42A VDD RC0/AD0 RC1/AD1 RC2/AD2 RC3/AD3 RC4/AD4 RC5/AD5 RC6/AD6 RC7/AD7

J 7894 HC

Abstract: AD7894-1
Contextual Info: 5V, 14-Bit, Serial 4.5jus ADC in 8-Pin Package ANALOG DEVICES Preliminary Technical Data FEATURES AD7894 FUNCTIONAL BLOCK DIAGRAM Fast 14 Bit ADC w i t h 4.5 |xs C o n v e r s i o n Ti me 8>Pin SOIC Package S i n g l e 5V S u p p l y O p e r a t i o n Hi gh Speed, Eas y - t o - Us e, Seri al I nt er f ac e

60-Channel

Abstract: HAS-1409KM HAS-1409 HAS-1409AKM HAS-1409LM HDD-1409 HDD-1409KM 1409AKM t50n
Contextual Info: 14-Bit, 125kHz Analog-to- Digita I Converter HAS-1409 ANALOG DEVICES FEATURES 14-Bit Resolution 125kHz Word Rates Internal Track-and-Hold 40-Pin DIP HAS-1409 FUNCTIONAL BLOCK DIAGRAM APPLICATIONS FDM/TDM Transmultiplexers CAT/NMR Scanners PCM Systems Digital Audio

VESUVIUS-LS

Abstract: ST 6x86
Contextual Info: PicoPoiverPT86C521 Vl-LS Pentium Processor PCI System Controller 1. V1-LS PIN INFORMATION 1.1 Pin Diagram CO O .0 ^ 0 1 ŒO % i o - - - * * * * * ^ *í l O % % % q_ 5 o O ~ ^f l^L L I0L L J0O ' * —0C M0C O 0 0 ^ , 5 , ^ oWO ^ O ç o ce 5 m SSSö8|g^8Sil^^S58^li|££££££8oSS3SS<<ö

Contextual Info: T R I Q U I N T S E M I C O N D U C T O R , I N C T O G A1086 Figure 1. Block Diagram FBIN S1 C LK SO NC NC GND 11-Output Clock Buffer Features • • Operates from 30 MHz to 67MHz P in-to-pin output skew o f 250 ps max • Period-to-period jitte r:

Contextual Info: M ic r o c h i p PIC16C72 SERIES 8-Bit CMOS Microcontrollers with A/D Converter D evices included: Pin Diagram s • PIC16C72 SDIP, SOIC, SSOP, W indowed Side Brazed Ceram ic • PIC16CR72 M icroco ntro ller C ore Features: MCLR/VPP-► E • High-perform ance RISC CPU