PIN CONFIGURATION 74LS10 Search Results

74LS10 pin configuration

Contextual Info: GD54/74LS10 TRIPLE 3-INPUT POSITIVE NAND GATES Description Pin Configuration This device contains three independent 3-input NAND gates. It performs the Boolean functions Y = A B C or Y = Â + B + Ü in positive logic. Vcc 1C 1Y 3C 3B 3A 3Y 14 13 12 11 10 9

74LS107AP

Abstract: 74LS107* pin and application
Contextual Info: MITSUBISHI LSTTLs M74LS107AP DUAL J-K NEGATIVE EDGE-TRIGGERED FLIP FLOPS WITH RESET DESCRIPTION PIN CONFIGURATION TOP VIEW The M 74LS107AP is a semiconductor integrated circuit containing 2 J-K negative edge-triggered flip -flo p circuits w ith discrete terminals fo r clock input T, J and K inputs

74LS109AP

Abstract: M74LS109 flip flop RS M74LS109AP
Contextual Info: MITSUBISHI LSTTLs M 74LS109A P DUAL J-K P O S IT IV E EDGE-TRIGGERED F L IP FLOP W IT H SET AND RESET DESCRIPTION PIN CONFIGURATION TOP VIEW The M74LS109AP is a semiconductor integrated circu it containing 2 J-K positive edge-triggered flip -flo p circuits

74ls163 function table

Contextual Info: GD54/74LS163A SYNCHRONOUS 4-BIT COUNTER: BINARY, SYNCHRONOUS CLEAR Feature • • • • • • Pin Configuration Internal Look-Ahead for Fast Counting Carry Output for n-Bit Cascading Synchronous Counting Synchronously Programmable Load Control Line Diode-Clamped Inputs

M74LS107AP

Abstract: 74LS107AP M74LS73AP 20-PIN 74ls107a 74LS107* pin and application
Contextual Info: M IT S U B IS H I LSTTLs M74LS107AP DUAL J-K NEGATIVE EDGE-TRIGGERED FLIP FLOPS W ITH RESET DESCRIPTION The PIN CONFIGURATION TOP VIEW M 74LS107A P conta in in g 2 J -K is a sem ico n d u c to r in teg rated c irc u it negative edge-triggered flip -flo p circuits

Contextual Info: GD54/74LS109A DUAL POSITIVE-EDGE- TRIGGERED J-K FLIP-FLOPS Feature Pin Configuration • Positive Edge-Triggering • Direct Set and reset inputs • J and K inputs • Q and Q outputs Vcc CLR2 J2 K2 C LK 2 PR2 Q2 QS R RRRFI R HR y Description This device contains two independent positiveedge-triggered J-K flip-flops with complementary out­

J-K Flip flops

Contextual Info: MITSUBISHI HIGH S P E E D CMOS M74HC107P/FP/DP DUAL J-K F L I P - F L O P WITH R E S E T DESCRIPTION The M74HC107 is a semiconductor integrated circuit con­ sisting of two negative-edge triggered J-K flip flops with in­ dependent control inputs PIN CONFIGURATION TOP VIEW

74LS10 mitsubishi

Contextual Info: M IT S U B IS H I HIGH SPEED CMOS M74HC10P/FP/DP T R IP L E 3 -IN P U T P O S IT IV E NAND GATE DESCRIPTION PIN CONFIGURATION TOP VIEW The M74HC10 is a semiconductor integrated circuit con­ sisting of three 3-input positive-logic NAND gates, usable as negative-logic NOR gates.

Contextual Info: MITSUBISHI HIGH SPEED CMOS M74HC10P M74HC10DP T R IP L E 3 -IN P U T P O S IT IV E NAND GATE DESCRIPTION The M 74H C 10 is a sem iconductor integrated c ircu it con­ sisting of three 3-in put p o s itiv e -lo g ic NAND, PIN CONFIGURATION TOP VIEW usable as

pin configuration 74LS10

Abstract: M74HC10P 4000B 74LS10 M74HC10 M74HC10DP of IC 74ls10 CMOS 74LS10 logic diagram of IC 74ls10 74LS10 mitsubishi
Contextual Info: M IT S U B IS H I HIGH S P E E D C M O S M74HC10P M74HC10DP T R IP L E 3 -IN P U T P O S IT IV E NAND G A TE DESCRIPTION The M 74H C 10 is a sem iconductor integrated circu it con­ sisting of three 3-input p o sitive-lo gic PIN CONFIGURATION TOP VIEW NAND, usable as

Contextual Info: MI TSUBI SHI HIGH S P E E D CMOS M74HC109P DUAL J-K F L I P - F L O P WI TH S E T AND R E S E T DESCRIPTION The M 74H C 109 is a sem iconductor integrated c irc u it con­ PIN CONFIGURATION TOP VIEW sisting of tw o po s itiv e -e d g e trig g e re d J -K flip -flo p s w ith in­

Contextual Info: M IT SU BISH I HIGH S P E E D CM O S & M74HC107P g v ' V\\'^ ' ste DUAL J-K F L I P - F L O P WITH R E S E T DESCRIPTION T he M 7 4 H C 1 0 7 is a sem ico n d u cto r integrated circuit co n­ PIN CONFIGURATION TOP VIEW sistin g of tw o n e g a tiv e -e d g e trig g ered J - K flip flo p s with in­

RS flip flop IC

Abstract: JK flip flop IC RS flip flop cmos Toggle flip flop IC M74HC109P 4000B 74LS109 M74HC109 RS flip flop
Contextual Info: M IT S U B IS H I HIGH S P E E D C M O S M 74H C 109P D U A L l- K F L IP -F L O P W IT H S E T A ND R E S E T DESCRIPTION The M 74H C 109 is a sem iconductor integrated c irc u it con­ PIN CONFIGURATION TOP VIEW sisting of tw o p o s itiv e -e d g e trig g e re d J -K flip -flo p s w ith in­

74HC109P

Contextual Info: MITSUBISHI HIGH S P E E D CMOS M 74H C 109P /FP /D P DUAL i-K F L I P - F L O P WITH S E T AND R E S E T DESCRIPTION T h e M 7 4 H C 1 0 9 is a s e m ic o n d u c to r in te g r a te d c irc u it c o n ­ PIN CONFIGURATION TOP VIEW s is tin g of tw o p o s it iv e -e d g e t r ig g e r e d J - K flip flo p s w ith in ­

Contextual Info: H D 74LS109A . •REC O M M EN D ED OPERATING Symbol Item /„O 'k Clock frequency Clock High P u lse width Sr.*.v* low “H "D ata Setup tim e “ L 'D a ta th Hold tim e Note 11 The arrow indicates the rising edge. Dual J-K Positive-edge-triggered Flip-Flops with Preset and Clear)

74LSOO

Abstract: 1S2074 HD74LS109A HD74LS109
Contextual Info: H D 74LS109A . Dual J-K Positive-edge-triggered Flip-Flops with Preset and Clear IP IN ARRANGEMENT •REC O M M EN D ED OPERATING CONDITIONS S ym bol Item fro c k C lock fre q u e n c y C lo c k High P u ls e w idth Sr.*.v* low “ H " D a ta S e tu p tim e

LM 7410

Contextual Info: Signetics I 7410, 7411, LS10, LS11, S10, S11 Gates Logic Products Triple Three-Input NAND ’10 , AND ('11) Gates Product Specification • TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT (TOTAL) 7410 9ns 6mA 74LS10 10ns 1.2mA 74S10 3ns 12mA 7411 10ns

TTL 7410

Abstract: 74LS11 function table 74LS10 pin configuration TTL 7410 AND propagation delay 7411 signetics
Contextual Info: Signetics I 7410, 7411, LS10, LS11 S10, S11 Gates Logic Products • Triple Three-Input NAND '10 , AND ('11) Gates Product Specification TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT (TOTAL) 7410 9ns 6mA 74LS10 10ns 1.2mA 74S1Û 3ns 12mA 7411 10ns

TTL 7411

Abstract: PIN CONFIGURATION 7410 74LS11 function table TTL LS 7411 74 LS 00 Logic Gates LS 7411 74LS10 pin configuration TTL 7410 TTL 7410 AND propagation delay PIN CONFIGURATION 74ls10
Contextual Info: Signetics I 7410, 7411, LS10, LS11, S10, S11 Gates Logic Products Triple Three-Input NAND '10 , AND ('11) Gates Product Specification I TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT (TOTAL) 7410 9ns 6mA 74LS10 10ns 1.2mA 74S10 3ns 12mA 7411 10ns 11mA

TTL 7410

Abstract: ua 7411 PIN CONFIGURATION 7410 PIN CONFIGURATION 7411 TTL 7411 74LS10 pin configuration 7411 pin configuration 74LS11 function table 74ls 7410 pin configuration
Contextual Info: Signetics I 7410, 7411, LS10, LS11, S10, S11 Gates Logic Products • Triple Three-Input NAND ’10 , AND ('11) Gates Product Specification TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT (TOTAL) 7410 9ns 6mA 74LS10 10ns 1.2mA 74S10 3ns 12mA 7411 10ns

R65F12Q

Abstract: R6501Q R65F11 rsc-forth pin configuration 74LS00 ROCKWELL R6501Q r6501 74LS04 pin configuration TTL 74ls00 pin configuration logic symbol 74LS00
Contextual Info: R65FRX • R65FKX R65FRX and R65FKx ^ -RSC FORTH Development and Kernel ROMS « Rockwell INTRODUCTION FEATURES The Rockwell Single Chip RSC FORTH System can be con­ figured using the R65F11, R65F12 microcomputers or the R6501Q ROM-less microcomputer. One of these microcom­

rockwell r65f11ap

Abstract: 65F12 pin configuration 74LS00 74LS00 pin configuration R65FR1P rockwell eprom R6501Q R65F12Q R65F1 Ram 2k x 32
Contextual Info: R65FRX • R65FKX * R65FRx and R65FKx RSC FORTH Development and Kernel ROMS Rockwell INTRODUCTION FEATURES The Rockwell Single Chip RSC FORTH System can be con­ figured using the R65F11, R65F12 microcomputers or the R6501Q ROM-less microcomputer. One of these microcom­

pin diagram of 74109

Abstract: 74109 74109 dual JK PIN CONFIGURATION 74109 TTL 74109 1N3064 1N916 74LS 74LS109 74LS109A
Contextual Info: 74109, LS109A Signetics Flip-Flops Dual J-K Positive Edge-Triggered Flip-Flop Product Specification Logic Products TYPICAL f MAX TYPICAL SUPPLY CURRENT TOTAL 74109 33MHz 9mA 74LS109A 33MHz 4mA DESCRIPTION The '109 is dual positive edge-triggered JK-type flip-flop featuring individual J, K,

8088 motherboard schematics

Abstract: Faraday motherboard 8088 PC XT MOTHERBOARD IBM computer schematics 8088 intel 8284 clock generator computer schematics 8088 c8087 ic 8237 dma controler 8088 ram 256K ic dma 8237 8088
Contextual Info: FARADAY 3486347 ELECTRONICS FARADAY INC A4 ELECTRONICS 00D0201 Í>F 34flL,3M7 CORP 84D 00201 h *|~D T- » '33 -03 T -5 2 - 3 3 -1 5 FE2010 PC BUS CPU & PERIPHERAL CONTROLLER IC * 100% Hardware & Software compatible to the IBM-PC * Keyboard Port * 8284 Clock Generator